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10 часов назад

Principal Digital RTL Engineer (Analog/Mixed-Signal)

185 000 - 240 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Principal Digital RTL Engineer (Analog/Mixed-Signal): Architecting and delivering high-performance analog and mixed-signal building blocks, including SerDes, PLLs, data converters, regulators, and references, for rack-scale AI connectivity silicon with an accent on performance, power, area, and production readiness. Focus on transistor-level design, PVT and Monte Carlo verification, layout collaboration, silicon bring-up, characterization, and technical mentorship.

Location: San Jose, California, United States — onsite

Salary: $185,000–$240,000 per year, depending on experience, level, and business need. The role may also be eligible for discretionary bonuses, incentives, and benefits.

Company

hirify.global develops rack-scale AI infrastructure through semiconductor connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

  • Architect, design, and optimize high-speed analog and mixed-signal circuits, including SerDes, PLLs, ADCs, DACs, LDOs, and bias/reference blocks.
  • Define block specifications and performance, power, area, and yield trade-offs for advanced process nodes.
  • Develop simulation plans across PVT, Monte Carlo, and reliability corners.
  • Partner with layout designers on floorplanning, matching, parasitics, and physical implementation.
  • Lead silicon bring-up, characterization, debugging, and correlation of measured results with models and specifications.
  • Set technical direction, improve AMS design methodologies, contribute to IP roadmaps, and mentor design engineers.

Requirements

  • MS or PhD in Electrical Engineering or a related field.
  • 8+ years of experience in analog/mixed-signal integrated circuit design.
  • Production-silicon experience designing high-speed AMS blocks such as SerDes, PLLs, data converters, references, or regulators.
  • Strong knowledge of transistor-level design, device physics, and analog fundamentals in advanced CMOS nodes.
  • Proficiency with Cadence Virtuoso, Spectre, and scripting for design automation.
  • Experience taking designs from specification through tape-out and silicon validation.

Nice to have

  • Experience with high-speed I/O and SerDes for PCIe, Ethernet, or UALink.
  • Knowledge of physical-layer signal integrity, channel modeling, and equalization.
  • Hands-on experience with high-speed measurement and characterization equipment.
  • Familiarity with mixed-signal verification and analog/digital co-design.
  • Strong communication skills and a collaborative, mentorship-oriented approach.

Culture & Benefits

  • Hands-on technical leadership in a fast-growing AI connectivity company.
  • Cross-functional collaboration with digital, system, product, packaging, and layout teams.
  • Opportunity to influence AMS design methodology, IP roadmaps, and design-flow improvements.
  • Discretionary bonus, incentives, and benefits may be available.
  • Applications are encouraged from candidates with diverse backgrounds and experiences.

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