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13 часов назад

I/O Architect (ASIC)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
I/O Architect (ASIC): Defining and developing NuLink PHY subsystems and protocol bridges for chiplet-based ASIC systems with an accent on PCIe, CXL, UCIe, AMBA, DDR, and RTL-to-GDSII implementation. Focus on performance modeling, protocol compliance, clock-domain and floorplan design, validation, and delivering manufacturable high-performance silicon.

Location: Bay Area, United States; on-site Monday through Friday

Company

hirify.global is an early-stage chiplet startup developing NuLink PHY technologies for high-performance, manufacturable chiplet-based systems.

What you will do

  • Define NuLink PHY physical and logical/link-layer subsystems and modular bridges across PCIe, AXI4, APB, CHI, CXL, and DDR.
  • Design protocol conversion layers covering transaction ordering, credit-based flow control, QoS, address translation, coherency, and memory semantics.
  • Model and optimize datapath, link protocols, and CDC architectures for bandwidth, latency, power, efficiency, and signal integrity.
  • Collaborate with ASIC, firmware, post-silicon, customer integration, and marketing teams while preparing architecture specifications and integration guidelines.
  • Review PLL, VCO, ATB, and link-training characterization plans and create protocol testbenches for transaction handling, throughput, latency, and compliance.
  • Mentor engineers, contribute to standards bodies, and improve design flows and methodologies for reliable on-time delivery.

Requirements

  • 8+ years of experience in architecture definition, chip micro-architecture, protocol definition, and implementation.
  • Strong knowledge of at least two connectivity protocols, including PCIe, UCIe, UALink, Ethernet, DDR, or AMBA.
  • Strong scripting and automation skills.
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • Expertise in RTL-to-GDSII flows, PHY implementation constraints, and practical logic design.

Nice to have

  • 15+ years of ASIC architecture experience and a track record of leading teams through successful tapeouts.
  • Performance modeling with C, C++, or SystemC.
  • Experience with PHY clocking and floorplan guidelines.
  • Exceptional problem-solving skills.

Culture & Benefits

  • Fast-paced early-stage startup environment.
  • Cross-functional collaboration with experienced industry specialists.
  • Opportunities to work on high-volume, high-performance, manufacturable chiplet products.
  • Fun work environment with excellent benefits.

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