14 часов назад
Senior Staff Design Engineer, IC Layout
158 700 - 238 100$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Staff Design Engineer, IC Layout (RFID/analog/mixed-signal ICs): Creating and integrating full-chip floorplans and transistor-level layouts for RFID products, reader ICs, test chips, and design-of-experiments silicon with an accent on tapeout execution, power integrity, signal integrity, and advanced-process layout. Focus on leading complex IC integration, resolving DRC/LVS and full-chip closure issues, and coordinating cross-functional teams through reliable, timely tape-outs.
Location: Remote, USA
Salary: $158,700–$238,100 base pay annually
Company
is a RAIN RFID and Internet of Things company developing silicon and connectivity solutions for billions of everyday items.
What you will do
- Create and refine RFID and reader IC floorplans using top-down and bottom-up methodologies.
- Collaborate with analog, digital, circuit, verification, packaging, manufacturing, and foundry teams on floorplanning, pin placement, power distribution, and routing.
- Coordinate layout and floorplan activities through predictable, high-quality tape-outs.
- Review power and ground routing, electromigration, matching, signal coupling, and signal integrity.
- Complete full-chip closure activities, including seal-ring and bump integration, dummy fill, DRC, LVS, density, and DFM checks.
- Perform transistor-level layout for RF, mixed-signal, and analog circuit blocks and contribute to the IC layout methodology roadmap.
Requirements
- Bachelor’s or master’s degree in computer engineering, electrical engineering, or a related technical field, plus 12+ years of experience.
- Experience with custom analog, RF, and mixed-signal layout and leading complex ICs from conception through tape-out.
- Expertise in full-chip or SoC-level floorplanning, integration, routing management, pin-ring generation, wafer assembly, and AOT and DOT methodologies.
- Knowledge of semiconductor manufacturing processes and foundry technologies down to 16 nm.
- Expertise with Cadence Virtuoso, Cadence and Siemens layout verification tools, PVS, Siemens Calibre DRC/LVS, and interpretation of ERC, DRC, and LVS reports.
- Ability to lead and mentor layout engineers, manage schedules, anticipate roadblocks, and collaborate with cross-functional teams.
Nice to have
- Experience with layout-dependent effects including noise coupling, matching, parasitics, LOD, WPE, PSE, and coloring.
- Knowledge of guard rings, DNW, PN junctions, parasitic management, EMIR, ESD, and signal-integrity mitigation techniques.
Culture & Benefits
- Remote work support or access to office facilities.
- Healthcare benefits and a 401(k) plan with company match for US-based employees.
- Potential eligibility for merit increases, annual bonuses, stock, and other rewards depending on role and performance.
- Open paid time off and emphasis on work-life balance.
- Open, collaborative, inclusive environment focused on innovation and teamwork.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →
Похожие вакансии
3 дня назад
Analog Mixed-Signal Layout Engineer (all gender)
7 дней назад
Analog Layout Design Engineer (Electrical Engineering)
109 380 - 154 420CAD
12 часов назад
Staff Photonics Design and Layout Engineer (Silicon Photonics)
175 000 - 210 000$
16 часов назад
Senior Mask Layout Engineer (Quantum Computing)
126 887 - 166 127$
7 дней назад
Senior Testchip SoC Physical Design Engineer (Integration & Methodology)
141 910 - 200 340$
8 часов назад
Electrical Engineer - PL (Quantum Computing Hardware)
113 000 - 150 000$