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14 часов назад

Senior Staff Design Engineer, IC Layout

158 700 - 238 100$
Формат работы
remote (только USA)
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US/Brazil
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Senior Staff Design Engineer, IC Layout (RFID/analog/mixed-signal ICs): Creating and integrating full-chip floorplans and transistor-level layouts for RFID products, reader ICs, test chips, and design-of-experiments silicon with an accent on tapeout execution, power integrity, signal integrity, and advanced-process layout. Focus on leading complex IC integration, resolving DRC/LVS and full-chip closure issues, and coordinating cross-functional teams through reliable, timely tape-outs.

Location: Remote, USA

Salary: $158,700–$238,100 base pay annually

Company

hirify.global is a RAIN RFID and Internet of Things company developing silicon and connectivity solutions for billions of everyday items.

What you will do

  • Create and refine RFID and reader IC floorplans using top-down and bottom-up methodologies.
  • Collaborate with analog, digital, circuit, verification, packaging, manufacturing, and foundry teams on floorplanning, pin placement, power distribution, and routing.
  • Coordinate layout and floorplan activities through predictable, high-quality tape-outs.
  • Review power and ground routing, electromigration, matching, signal coupling, and signal integrity.
  • Complete full-chip closure activities, including seal-ring and bump integration, dummy fill, DRC, LVS, density, and DFM checks.
  • Perform transistor-level layout for RF, mixed-signal, and analog circuit blocks and contribute to the IC layout methodology roadmap.

Requirements

  • Bachelor’s or master’s degree in computer engineering, electrical engineering, or a related technical field, plus 12+ years of experience.
  • Experience with custom analog, RF, and mixed-signal layout and leading complex ICs from conception through tape-out.
  • Expertise in full-chip or SoC-level floorplanning, integration, routing management, pin-ring generation, wafer assembly, and AOT and DOT methodologies.
  • Knowledge of semiconductor manufacturing processes and foundry technologies down to 16 nm.
  • Expertise with Cadence Virtuoso, Cadence and Siemens layout verification tools, PVS, Siemens Calibre DRC/LVS, and interpretation of ERC, DRC, and LVS reports.
  • Ability to lead and mentor layout engineers, manage schedules, anticipate roadblocks, and collaborate with cross-functional teams.

Nice to have

  • Experience with layout-dependent effects including noise coupling, matching, parasitics, LOD, WPE, PSE, and coloring.
  • Knowledge of guard rings, DNW, PN junctions, parasitic management, EMIR, ESD, and signal-integrity mitigation techniques.

Culture & Benefits

  • Remote work support or access to office facilities.
  • Healthcare benefits and a 401(k) plan with company match for US-based employees.
  • Potential eligibility for merit increases, annual bonuses, stock, and other rewards depending on role and performance.
  • Open paid time off and emphasis on work-life balance.
  • Open, collaborative, inclusive environment focused on innovation and teamwork.

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