Semiconductor Product Engineering Team Leader (AI)

Location: Bristol, United Kingdom

Company

hirify.global develops chips and systems designed to accelerate inference for frontier AI models.

What you will do

• Drive manufacturing test strategy and silicon production readiness for next-generation AI accelerator devices.
• Lead product engineering teams through test planning, program development, pattern bring-up, silicon characterization, debug, and optimization.
• Manage OSATs, ATE vendors, and external engineering partners, including scope, schedules, technical oversight, and quality control.
• Define test software architecture, DFT usage, and structural and functional test strategies for logic, SRAM, DRAM, and high-speed I/O.
• Lead ATE silicon bring-up, correlation, failure analysis, corner and stress testing, shmooing, and yield improvement.
• Support advanced packaging test, qualification, reliability testing, and high-volume manufacturing transfer.

Requirements

• BS, MS, or PhD in Electronics and Electrical Engineering or a related field.
• 8+ years of semiconductor test engineering experience, including leadership or technical lead responsibilities.
• Experience with ATE test development using Advantest 93K, Teradyne Ultraflex, or similar platforms.
• Strong knowledge of DFT, including scan, ATPG, LBIST, and MBIST, plus memory and high-speed interface testing.
• Experience managing external test development partners or OSATs and leading test engineering teams.
• Background in advanced CMOS nodes, advanced packaging test, silicon debug, characterization, and ATE-to-system correlation.

Nice to have

• Experience with AI/ML accelerator chips or other high-performance compute ICs.
• Experience with PCIe Gen5/Gen6 or LPDDR4/5/6 test methodologies.
• Knowledge of signal-integrity-aware test development and high-speed I/O margining.
• Experience with chiplets, 2.5D/3D IC test flows, or heterogeneous integration.

Culture & Benefits

• High ownership and direct collaboration with top leadership.
• Rapid iteration from ideas to hardware on ambitious timelines.
• Close collaboration across hardware, software, silicon, and modelling teams.
• Meaningful equity and competitive compensation.
• Private medical, dental and vision coverage, contributory pension, 25 days of holiday plus bank holidays, and life/critical illness insurance.
• Inclusive and diverse office environment.

Hiring process

• Additional eligibility checks may be required because the work is subject to UK, US, and other international export control regulations.