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14 часов назад

Advanced Packaging Engineer, Principal (Photonics)

185 000 - 240 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Advanced Packaging Engineer, Principal (Photonics): Leading advanced packaging R&D for next-generation photonics products used in scale-up and scale-out AI infrastructure with an accent on 2.1D, 2.5D, and 3D integration, optical chip packaging, and EIC-to-PIC integration. Focus on developing wafer-, panel-, and die-level process flows, qualifying materials and equipment, improving yield and reliability, and authoring packaging PDKs and design rules for NPO and CPO products.

Location: San Jose, California, United States; on-site

Salary: $185,000–$240,000 per year, depending on experience, level, and business need. The role may also include a discretionary bonus, incentives, and benefits.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software for hyperscalers and ecosystem partners.

What you will do

  • Lead advanced packaging R&D for optical chips and next-generation NPO and CPO products.
  • Define and optimize wafer-level, panel-level, and die-level packaging process flows, including 2.1D, 2.5D, and 3D integration.
  • Drive EIC-to-PIC integration and optical device integration efforts.
  • Select and qualify advanced packaging materials while partnering with OSATs, tool vendors, and material suppliers.
  • Characterize and improve package yield, reliability, and process capability.
  • Develop and maintain packaging PDKs and design rules.

Requirements

  • B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
  • 8+ years of semiconductor or advanced packaging engineering experience with demonstrated technical leadership.
  • Deep expertise in 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and overmold processes.
  • Experience with silicon photonics chip packaging, EIC/PIC integration, and advanced packaging materials.
  • Experience qualifying equipment and processes with OSATs or tool suppliers.
  • Experience with PDK development, packaging design rules, yield analysis, reliability characterization, Cpk, and SPC.

Nice to have

  • Hands-on CPO or NPO product development experience.
  • Experience with optical coupling or waveguide alignment for photonic integration.
  • Familiarity with photonics chip design, photonics devices, DFM, and DFT.

Culture & Benefits

  • Discretionary bonus and incentive eligibility may be available.
  • Benefits are included as part of the compensation package.
  • Inclusive environment welcoming diverse backgrounds and experiences.

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