Назад
Company hidden
3 дня назад

Principal Analog Mixed Signal ASIC Layout Engineer (CMOS)

95 000 - 245 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Principal Analog Mixed Signal ASIC Layout Engineer (CMOS): Creating custom analog layouts, floor-planning entire chips, and supporting tape-outs for ASICs used in national security, biomedical, and space applications with an accent on full-custom layout, circuit performance, and physical verification. Focus on designing low-power and advanced-node CMOS layouts, debugging DRC/LVS and extracted-parasitic effects, and solving complex chip architecture and layout challenges independently.

Location: Cambridge, Massachusetts, United States; mandatory on-site work

Salary: $95,000–$245,000 base salary per year

Company

hirify.global is an independent, nonprofit research and development company delivering engineering solutions for national security, biomedical engineering, and space applications.

What you will do

  • Create custom analog mixed-signal ASIC layouts from schematics and perform chip-level floor planning.
  • Design and simulate transistor-level circuits and contribute to system-level architectures.
  • Optimize hardware designs for performance, power, and cost while evaluating complex algorithm requirements.
  • Perform physical layout and simulate extracted parasitics, including debugging physical verification issues.
  • Drive solutions to complex and changing technical requirements across disciplines.
  • Develop design specifications, contribute to proposals, and mentor less experienced engineers.

Requirements

  • Bachelor’s degree in Engineering or a related field; a master’s degree is preferred.
  • 5–7 years of ASIC hardware engineering experience with a bachelor’s degree, 3–5 years with a master’s degree, or 0–2 years with a PhD.
  • Proficiency in integrated circuit design, semiconductors, computer architecture, mathematics, and technical documentation.
  • Experience implementing analog designs in full-custom layout, including PLLs, DACs/ADCs, high-speed SerDes, bandgaps, and ESD/IO.
  • Experience with low-power design, advanced CMOS nodes below 32 nm, radiation-hardened electronics, and physical verification methodologies such as DRC, LVS, and PM.
  • Ability to work on site in Cambridge and obtain and maintain a government security clearance.

Nice to have

  • Experience with FinFET, GAAFET, photonics, 22 nm to 7 nm and below processes, reticle design, or MPW aggregation.
  • Experience with Cadence Virtuoso, Pegasus, ModGen, autorouter, EAD, Innovus, Siemens Calibre, and Keysight SOS.
  • Experience with SKILL, SVRF, Tcl, Linux, Git, SVN, or other automation and revision-control tools.
  • Experience with top-down floor planning, abstract/LEF data transfer, and mentoring engineers.

Culture & Benefits

  • Collaborative multidisciplinary work across engineering and scientific teams.
  • Workplace flexibility programs and initiatives supporting work-life balance.
  • Employee clubs, including photography and yoga.
  • Health and finance workshops, off-site social events, and discounts to local museums and cultural activities.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →