Design Verification Engineer (UVM)

Location: Santa Clara, California, United States

Salary: $86,950–$130,100 per annum

Company

hirify.global develops semiconductor solutions for enterprise, cloud and AI, and carrier data infrastructure.

What you will do

• Verify circuitry for high-speed data-transfer chips against customer and architectural specifications.
• Understand PCIe and memory subsystem architecture and functionality.
• Develop and maintain UVM-based verification environments.
• Define and review verification test plans with architecture and design teams.
• Run regression tests, debug simulation failures, and verify randomized functional parameters.
• Report coverage and drive verification coverage toward the 100% target.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 1–3 years of related experience, or a relevant master’s degree.
• Coursework or projects covering analog circuits, Verilog or VHDL, basic circuits, computer architecture, and VLSI or chip design.
• Experience using Synopsys, Cadence, or Mentor tools for simulation and writing and debugging testbenches.
• Comfort working in a Linux environment and scripting with Python.
• Strong attention to detail and willingness to iteratively refine designs.
• Ability to communicate progress, issues, and schedule deviations effectively with the team.

Culture & Benefits

• Opportunities to learn, grow, and contribute ideas as an early-career engineer.
• Employee stock purchase plan with a two-year lookback.
• Family support programs and mental and physical health resources.
• Recognition and service awards for contributions and milestones.
• Employment is subject to U.S. export control eligibility and possible export license review.

Hiring process

• Interview process evaluates individual experience, thought process, and communication.
• AI tools, transcription apps, automated note-taking bots, and real-time answer generators are not permitted during interviews.