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4 часа назад

Senior Staff PCB Layout Design Engineer (AI Hardware)

175 000 - 265 000$
Формат работы
hybrid/onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Staff PCB Layout Design Engineer (AI Hardware): Leading high-complexity PCB and PCBA layouts for AI accelerator cards and system baseboards with an accent on 112G/224G SerDes integrity, power delivery, and constraint management. Focus on designing 20+ layer boards, automating Cadence Allegro workflows with SKILL or Python, and meeting DFM, DFT, and DFA requirements for high-yield production.

Location: Santa Clara, CA, United States; hybrid/on-site

Salary: $175,000–$265,000 annually, plus equity and incentive opportunities

Company

hirify.global develops software and hardware platforms for generative AI and Digital In-Memory Computing.

What you will do

  • Lead full-cycle PCB layout for high-complexity AI accelerator cards and system baseboards with 20+ layers.
  • Architect and manage Cadence Allegro Constraint Manager hierarchies for high-speed routing, physical spacing, and electrical constraints.
  • Develop or implement SKILL, Python, or TCL automation for layout tasks, DRC checks, design audits, and reporting.
  • Route PCIe Gen5/6, CXL, custom die-to-die interconnects, 112G/224G SerDes, DDR5, and HBM interfaces.
  • Optimize power delivery networks, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICs.
  • Define PCB stack-ups and materials, coordinate with fabricators and contract manufacturers, and ensure DFM, DFT, and DFA requirements.

Requirements

  • BS degree in Electrical or Electronic Engineering, or equivalent practical experience.
  • 12+ years of high-speed, high-density PCB layout experience for servers, networking systems, or AI accelerators.
  • Expert proficiency with Cadence Allegro Constraint Manager, including T-junctions, differential-pair phase tuning, and Z-axis delay matching.
  • Experience writing and deploying SKILL scripts or using the Allegro API to automate design audits and layout routines.
  • Deep knowledge of back-drilling, via-in-pad, skip-vias, HDI, and ELIC technologies.
  • Ability to work in a hybrid/on-site role based in Santa Clara, California.

Nice to have

  • Experience establishing library management systems and standardized footprint and padstack processes.
  • Familiarity with PLM/PDM integration, layout releases, and ECO workflows.
  • Knowledge of PCB warpage mitigation for large-form-factor ASICs and MCMs.
  • Experience with low-loss materials such as Megtron 7/8 and hybrid PCB build-ups.

Culture & Benefits

  • Collaborative and inclusive environment centered on respect, humility, and direct communication.
  • Autonomy to build layout infrastructure, automation, and design methodology from the ground up.
  • Medical, dental, and vision coverage.
  • 401(k), equity, and performance-based incentive opportunities.
  • Benefits focused on employee and family wellbeing.

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