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6 дней назад

System Performance Modeling Engineer/Architect (AI)

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Singapore
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
System Performance Modeling Engineer/Architect (AI): Building full-chip performance models for AI and Bitcoin-mining accelerator architectures with an accent on tile arrays, NoC behavior, memory bandwidth, and power-aware performance trade-offs. Focus on modeling contention and workloads, correlating predictions with RTL and silicon, and turning quantitative analysis into architecture decisions.

Location: Singapore

Company

hirify.global is a technology company focused on Bitcoin mining, ASIC hardware, high-performance computing, and AI cloud infrastructure.

What you will do

  • Build and maintain cycle-approximate and analytical full-chip models of tile arrays, NoC, and memory subsystems using C++, SystemC, and Python.
  • Perform workload mapping, roofline analysis, bottleneck analysis, and traffic modeling across the tile array and memory hierarchy.
  • Evaluate architecture trade-offs involving tile count, local memory, NoC topology and bandwidth, memory channels, and QoS.
  • Correlate model predictions against RTL, emulation, FPGA implementations, and later silicon to reduce the modeling-to-reality gap.
  • Provide golden-reference hooks for performance and verification sign-off.
  • Maintain dashboards and trade-off reports for architecture and program leadership.

Requirements

  • 5+ years of experience in performance modeling or architecture for SoCs and accelerators.
  • Strong C++ and Python skills, with experience in SystemC or a comparable cycle-approximate modeling framework.
  • Strong knowledge of memory hierarchies, bandwidth and latency trade-offs, interconnect and NoC behavior, and roofline analysis.
  • Ability to model subsystems and translate quantitative results into architecture decisions.
  • Experience working with incomplete specifications and collaborating across architecture, design, and software teams.

Nice to have

  • Experience with NoC or interconnect modeling, memory-controller behavior, or 3D-DRAM/HBM bandwidth analysis.
  • Exposure to compiler and dataflow co-design for accelerators.
  • Experience correlating models against RTL, emulation, FPGA, or silicon results.
  • Background in tile-based or dataflow architectures.

Culture & Benefits

  • Inclusive environment that values diverse perspectives and backgrounds.
  • Startup-oriented, fast-growing environment with opportunities to work on new projects and systems.
  • Autonomy, personal accountability, professional growth, and learning opportunities.
  • Training, mentoring, welfare benefits, and opportunities to contribute to digital asset and AI infrastructure.

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