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2 месяца назад

ASIC Layout Engineer (A OT AESS)

Формат работы
onsite
Тип работы
fulltime
Грейд
middle
Английский
c1
Страна
Romania
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
ASIC Layout Engineer (A OT AESS) (Analog Semiconductor Layout): Creating and integrating robust analog block and chip layouts for semiconductor solutions in Timisoara with an accent on floor planning, pin placement, parasitic extraction, and efficient area utilization. Focus on achieving DRC-compliant layouts, addressing deep-submicron effects, and supporting speed, power, DFM, ESD/EMV, and tape-out requirements.

Location: Timisoara, Romania

Company

Automotive technology company developing and manufacturing hardware, software, services, and fabless semiconductor solutions for the future of mobility.

What you will do

  • Create and integrate analog layouts at block and top level.
  • Perform floor planning, pin placement, and parasitic extraction.
  • Work closely with analog circuit designers and support design engineers.
  • Optimize layouts for speed, area, power, DFM, and ESD/EMV requirements.
  • Support DRC, LVS, and tape-out activities.

Requirements

  • Master of Science or PhD in Electrical Engineering, Microelectronics, Physics, or a similar field.
  • Bachelor's degree in Electronics Engineering.
  • At least 2 years of layout design experience.
  • Strong knowledge of analog circuit layout and deep-submicron effects, including parasitics, coupling, and matching.
  • Basic knowledge of layout design, DRC, LVS, extraction tools, and analog circuit design.
  • Fluent English required.

Nice to have

  • Experience creating layouts in BCD technology, particularly at 65–180 nm.

Culture & Benefits

  • Opportunity to work on semiconductor solutions supporting the future of mobility.
  • Collaborative work with analog circuit and design engineers.
  • Culture focused on ownership, initiative, professional growth, and meaningful impact.

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