Principal Engineer (ASIC Verification)

TL;DR

Principal Engineer (ASIC Verification) (SystemVerilog/UVM): Performing semiconductor design verification and testing for mixed-signal devices in the electronic communications industry with an accent on UVM environments, digital and top-level simulations, and coverage-driven verification. Focus on developing verification infrastructure, debugging GLS simulations, managing regressions, and achieving complete coverage before tape-out.

Location: Onsite in Chandler, United States

Salary: $174,070 per year.

Company

hirify.global develops semiconductor products and devices for electronic communications and related applications.

What you will do

• Design, develop, and test semiconductor products and devices.
• Participate in digital functional verification of mixed-signal circuit designs.
• Develop UVM simulation environments, including drivers, monitors, checkers, and assertions.
• Run digital and top-level simulations and maintain regression test suites.
• Define IP test specifications with design leaders and ensure complete coverage before tape-out.
• Report and resolve bugs, track verification artifacts, and lead design verification reviews.

Requirements

• Bachelor’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, VLSI, Physics, or a related field.
• Five years of progressive post-baccalaureate experience in engineering, design engineering, verification engineering, or a closely related role.
• Experience with ARM processors and multiprocessor interaction.
• Experience with SystemVerilog, UVM verification, ASIC design verification, and SoC testbenches.
• Experience with I2C, SPI, SPMI, and UART serial communication protocols.
• Experience with GLS simulation and debugging, regression management, artifact tracking, and C-based test development.

Culture & Benefits

• Equal opportunity and affirmative action employment.
• Reasonable accommodations are provided for otherwise qualified individuals with disabilities.