DFT Engineer/Leader (ASIC)

TL;DR

DFT Engineer/Leader (ASIC): Implementing and optimizing design-for-test architectures for advanced ASIC chips with an accent on boundary scan, MBIST, JTAG, scan ATPG, and test compression. Focus on validating post-gate designs, resolving timing and congestion challenges, and delivering production-ready test patterns through ATE debugging.

Location: Singapore, SG

Company

hirify.global develops Bitcoin mining infrastructure, ASIC chips, mining rigs, datacenters, and AI cloud capabilities.

What you will do

• Implement and optimize boundary scan, MBIST, test logic insertion, and JTAG solutions.
• Develop and validate scan ATPG and compression methodologies.
• Conduct DFT and post-gate simulations and generate constraints to ensure robust, efficient testing.
• Deliver test patterns and collaborate with test teams on ATE debugging.
• Use EDA tools such as Tessent to improve test processes and efficiency.
• Provide technical mentorship and guidance to junior engineers.

Requirements

• Bachelor’s, Master’s, or PhD degree in Electrical Engineering or Computer Engineering.
• At least 8 years of relevant DFT experience.
• Proficiency with synthesis tools such as Genus or Design Compiler.
• Experience creating test plans and strategies in collaboration with design teams.
• Experience supporting DFT insertion and resolving DFT-related timing or congestion challenges with implementation teams.
• Strong drive, attention to detail, and collaborative skills.

Culture & Benefits

• Inclusive environment that values authenticity and diverse perspectives.
• Start-up spirit in a fast-growing technology company.
• Opportunities to contribute directly to digital asset and AI infrastructure projects.
• Autonomy, personal accountability, and opportunities for rapid growth.
• Training, mentoring, welfare benefits, and professional development opportunities.