Asic/Fpga Methodology Engineer (Embedded)

TL;DR

ASIC/FPGA Methodology Engineer (Embedded): Defining and maintaining methodologies and workflows for FPGA and ASIC design and verification with an accent on RTL design, tool optimization, and CI/CD integration. Focus on implementing automated pipelines, solving complex hardware debugging issues, and ensuring timing closure for high-performance designs.

Location: North Reading, MA, US

Salary: $154,900–$247,800

Company

Global test and automation specialists providing sophisticated solutions that ensure electronic devices work correctly through advanced manufacturing automation.

What you will do

• Develop and maintain methodologies for ASIC/FPGA design, verification, and implementation.
• Collaborate with design and verification teams to ensure seamless integration of workflows and tools.
• Support the development of RTL designs using Verilog and debug complex hardware issues.
• Optimize design flows for FPGA tools such as Vivado and Quartus.
• Implement and manage CI/CD pipelines using Jenkins, Docker, and Git.
• Provide technical guidance and training to team members on hardware design best practices.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of industry experience in FPGA and embedded design.
• Hands-on experience with FPGA development tools (Vivado, Quartus) and ASIC design flows.
• Proficiency in Git, Docker, LSF, Jenkins, Artifactory, and Clearcase.
• Understanding of digital design verification methodologies such as SystemVerilog and UVM.
• Experience with timing analysis, synthesis, and timing closure for FPGA/ASIC designs.

Culture & Benefits

• Comprehensive health and well-being programs including medical, dental, and vision.
• Retirement savings plans and life/disability insurance.
• Paid vacation, holidays, and tuition assistance programs.
• Flexible Spending Accounts (FSA).
• Inclusive work environment focused on creativity and diversity of thought.