Physical Design Methodology Engineer (AI HW IP)

TL;DR

Physical Design Methodology Engineer (AI HW IP): Develops, deploys, and owns RTL-to-GDSII flows for AI accelerator and high-performance CPU IP with an accent on EDA automation, advanced-node methodology, and repeatable PPA exploration. Focus on qualifying new technology nodes and EDA releases, integrating ML-driven optimization, and ensuring production-ready physical design and signoff flows.

Location: Hybrid, based in Toronto, Ontario, Canada; Austin, Texas, United States; or Belgrade, Serbia. Employment may be contingent on eligibility to access U.S. export-controlled technology and, where applicable, obtaining prior license approval.

Salary: $100,000–$500,000, including base and variable compensation targets.

Company

Tenstorrent develops AI computing platforms combining AI software, compilers, networking, semiconductors, and high-performance RISC-V CPUs.

What you will do

• Develop, deploy, and own RTL-to-GDSII physical design methodology and CAD flows.
• Automate manual steps and make PPA exploration repeatable for production teams.
• Stand up flows for new technology nodes, PDKs, foundry targets, and customer variants.
• Qualify new EDA tool releases and support production physical design teams.
• Collaborate with design teams and EDA vendors, documenting flows for independent use.
• Apply AI, LLMs, and ML-driven optimization where they provide measurable value.

Requirements

• 5+ years of experience developing and supporting production physical design methodology or CAD flows.
• Experience with Fusion Compiler, ICC2, Innovus, Genus, PrimeTime, and RedHawk.
• Strong scripting skills in Tcl, Python, and Perl.
• Deep knowledge of advanced-node methodology, UPF/CPF low-power intent, clock tree synthesis, and EM/IR and DRC/LVS signoff.
• Experience preparing flows for new technology nodes, PDKs, or foundry targets and qualifying EDA releases.
• Eligibility to access U.S. export-controlled technology may be required.

Nice to have

• Experience with AI accelerators and high-performance CPUs on advanced FinFET or GAA nodes.
• ML-driven flow optimization or custom CAD development experience.
• Experience influencing EDA vendor roadmaps through technical partnerships.
• Experience with multi-variant, multi-foundry IP delivery.

Culture & Benefits

• Collaborative environment focused on curiosity and solving technically difficult problems.
• Opportunity to work on AI computing platforms and production-scale EDA automation.
• Competitive compensation package and benefits.
• Equal opportunity employment.