Digital IC Design Engineer (AI Hardware)

TL;DR

Digital IC Design Engineer (AI Hardware): Designing and verifying custom digital hardware components and architectures for tightly integrated, high-performance AI and semiconductor workloads with an accent on RTL design, functional verification, and hardware-software co-design. Focus on building memory, control, and compute subsystems, solving complex integration and timing challenges, and interfacing custom tensor processing units.

Location: On-site in Paris, France, or Tel Aviv, Israel. Relocation support is available for moves within 20 minutes of the company location.

Company

An early-stage AI and computer hardware startup developing technologies at the intersection of artificial intelligence and semiconductors.

What you will do

• Design, implement, and verify RTL blocks for memory, control, and compute subsystems.
• Define block-level specifications with system software and architecture teams.
• Develop functional verification infrastructure for simulation and hardware testbenches.
• Support synthesis, timing analysis, and backend integration with physical design and CAD engineers.
• Contribute to architectural exploration and hardware-software co-design for future compute platforms.

Requirements

• Extensive RTL design experience with Verilog and SystemVerilog.
• Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system integration.
• Experience developing testbenches, assertions, coverage metrics, and debugging functional verification issues.
• Familiarity with ASIC and FPGA flows, synthesis, timing closure, and DFT.
• Ability to work across architectural specification, microarchitecture, and physical implementation support.
• Proficient English is required; French is optional.

Nice to have

• UVM experience.

Culture & Benefits

• Competitive cash compensation based on location, experience, and internal pay equity.
• Stock options included in the majority of full-time offers.
• Relocation bonus and moving expense coverage.
• Healthcare coverage, pension contributions, professional development support, 25 days of paid time off, and public holidays.
• Engineering-led, fast-paced, multicultural environment with ownership of a key technical domain.
• Reimbursement of 50% of the public transport subscription fee.

Hiring process

• Screening call followed by a technical meeting.
• CEO interview, reference calls with former managers, and a role-specific take-home technical assessment.
• Final interview to discuss the technical assignment and remaining questions.