Digital Design Verification Engineer (SystemVerilog)

TL;DR

Digital Design Verification Engineer (SystemVerilog): Ensuring the functional integrity, performance, and reliability of next-generation optical chips with an accent on UVM environments, ASIC verification, and high-speed interface validation. Focus on designing coverage-driven testbenches, verifying PCIe and RISC-V subsystems, performing timing-accurate netlist simulations, and supporting pre- and post-silicon validation.

Location: On-site at offices in Paris, France, or Tel Aviv, Israel. Relocation support is available for moves within 20 minutes of the company location.

Company

An early-stage AI and computer hardware company developing technologies at the intersection of artificial intelligence and semiconductors, with a multidisciplinary team of engineers and scientists.

What you will do

• Develop verification plans for complex digital and mixed-signal optical chip designs.
• Build and optimize SystemVerilog and UVM testbenches with constrained-random testing, assertions, transaction-level modeling, regression automation, and functional coverage.
• Verify PCIe-based digital blocks using protocol checking, compliance validation, error injection, and protocol analysis.
• Verify RISC-V CPU cores and subsystems through reference-model comparisons, signature checks, formal verification, compliance suites, and edge-case testing.
• Perform block-level, subsystem, and full-chip ASIC verification, including SDF-annotated netlist simulations and coverage analysis.
• Collaborate with architects, designers, customers, and cross-functional teams to debug issues and support FPGA/ASIC bring-up and post-silicon validation.

Requirements

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Hands-on expertise in SystemVerilog and prior experience with the UVM framework.
• Knowledge of AXI/AXIStream, APB/AHB, I2C, JTAG, and PCIe protocols.
• Experience verifying RISC-V CPU designs or equivalent processor architectures in an ASIC context.
• Proficient English required; French is an advantage.
• Strong analytical, communication, ownership, and risk-management skills in fast-paced collaborative environments.

Nice to have

• Experience with formal verification, protocol analyzers, and compliance validation.
• Experience supporting FPGA/ASIC bring-up and post-silicon validation.

Culture & Benefits

• Engineering-led, multicultural startup environment with high velocity and close collaboration.
• Competitive cash compensation based on location, experience, and internal pay alignment.
• Stock options included in most full-time offers.
• Relocation bonus and moving-expense coverage for eligible relocation.
• Healthcare, pension contributions, professional development support, 25 days of paid time off, and public holidays.
• Reimbursement of 50% of the public transport subscription fee.

Hiring process

• Screening call followed by a technical meeting about past projects and achievements.
• Take-home technical assessment, followed by a final discussion with team members.
• CEO interview and mandatory reference calls with former managers.