Mixed Signal Validation Engineer (System Verilog)

TL;DR

Mixed Signal Validation Engineer (System Verilog): Performing pre-silicon functional validation for mixed signal designs and integrated circuitry with an accent on validation coverage, power, and area goals. Focus on developing validation infrastructure, performing root-cause debug of triage failures, and optimizing mixed signal interfaces.

Location: Hybrid (US, California: Folsom or Santa Clara). Regular onsite presence is required.

Salary: $122,440 - $172,860 USD

Company

hirify.global is a global leader in semiconductor design and manufacturing.

What you will do

• Define and execute pre-silicon functional validation for mixed signal designs and components.
• Develop validation methodologies and infrastructure, including monitors and behavioral checkers.
• Perform debug and root-cause analysis to resolve functional and triage failures.
• Collaborate with architecture and design teams to optimize mixed signal interfaces.
• Review design changes to assess impact on validation plans and timelines.
• Publish comprehensive validation reports and communicate findings to stakeholders.

Requirements

• Bachelors in Computer Science, Electrical Engineering, or STEM with 3+ years' experience, OR Masters with 6+ months' experience.
• Experience in IP or SoC development/verification using System Verilog, OVM, or UVM.
• Proven ability to write and implement detailed validation plans using System Verilog.
• Must be based in the US and able to work in a hybrid model with regular onsite presence in Folsom or Santa Clara, CA.

Nice to have

• 2+ years of experience with DFI, DDR, or LPDDR protocols.
• Experience with DDR Phy or Memory Controller verification.

Culture & Benefits

• Competitive compensation package including stock bonuses.
• Comprehensive health, retirement, and vacation programs.
• Hybrid work model allowing split time between on-site and off-site work.