Silicon Packaging Design Engineer (Hardware)

TL;DR

Silicon Packaging Design Engineer (Hardware): Driving the end-to-end development of test boards for advanced silicon package validation with an accent on board design execution, package-board integration, and manufacturability. Focus on optimizing signal integrity, power delivery, and resolving complex DRC violations to ensure high-performance semiconductor hardware.

Location: On-site presence required in Phoenix, AZ or Hillsboro, OR

Salary: $164,470 - $232,190 USD

Company

hirify.global is a global leader in semiconductor manufacturing and silicon packaging innovation.

What you will do

• Drive end-to-end development of test board designs from concept through tapeout.
• Perform board planning, floor planning, routing studies, and physical layout implementation.
• Partner with package design, test engineering, and validation teams to optimize package-board interactions.
• Conduct design rule checks (DRCs) and validate manufacturing design rules to ensure successful fabrication.
• Collaborate with board fabrication and assembly vendors to obtain design approval.
• Maintain board design guidelines and release collateral within PLM systems.

Requirements

• Master's degree in Electrical Engineering or Mechanical Engineering.
• 10+ years of experience with PCB layout utilizing Cadence Allegro and Cadence Constraint Manager.
• 5+ years of experience in hardware development, including Schematic Entry, Signal Integrity, and Power Delivery.
• Expertise in interconnect methodologies, DFM, DFX, and manufacturability principles.
• This position is not eligible for immigration sponsorship.

Nice to have

• Experience with PCB design tools such as Siemens Xpedition.
• 8+ years of experience with HDI/Type4 PCB technology.
• Proven track record of managing external CAD contract workers.
• Experience managing multi-disciplined teams in a dynamic, fast-paced environment.

Culture & Benefits

• Competitive pay and stock bonuses.
• Comprehensive benefit programs including health, retirement, and vacation.
• Opportunity to work on cutting-edge silicon packaging in a high-volume semiconductor environment.