Senior Principal Engineer (Digital IC Design)

TL;DR

Senior Principal Engineer (Digital IC Design): Developing high-performance integrated circuits and ASIC architectures for data infrastructure with an accent on signal processing and communications algorithms. Focus on RTL implementation, synthesis, timing closure, and post-silicon debug for high-speed DSP physical layer products.

Location: Must be based in Boise, ID

Salary: $214,000–$244,000 per year

Company

hirify.global is a leading semiconductor company providing essential data infrastructure solutions across enterprise, cloud, AI, and carrier architectures.

What you will do

• Develop ASIC specifications and micro-architectures for signal processing and communications algorithms.
• Perform high-speed data path RTL implementation using Verilog, synthesis, and backend flows.
• Specify and implement digital features and integrate vendor IP.
• Conduct post-silicon debug, correlation, and functional validation in a lab environment.
• Execute static timing analysis, formal equivalence, and cross-clock domain (CDC) analysis.
• Mentor junior team members and assist in design automation for CAD EDA flows.

Requirements

• Bachelor’s degree or foreign equivalent in Electrical/Electronic Engineering, Computer Science, or related field.
• Minimum 5 years of experience in digital/mixed-signal IC design at 16nm or smaller technology nodes.
• Proven expertise in the entire design cycle from micro-architecture to post-silicon debug.
• Proficiency in Verilog, System Verilog, Perl, and Unix Shell.
• Experience with high-speed DSP physical layer products for datacenter applications.
• Must be eligible to access export-controlled information under U.S. law.

Culture & Benefits

• Competitive compensation package with comprehensive benefits.
• Collaborative, transparent, and inclusive work environment.
• Access to resources for professional growth and long-term career development.
• Opportunity to work on industry-leading semiconductor technology.