Sr Principal Design Engineer (FPGA)

TL;DR

Sr Principal Design Engineer (FPGA/RTL): Designing and productizing high-performance protocol products like PCIe and advanced Ethernet for flagship emulation and prototyping lines with an accent on logic RTL design and UVM-based verification. Focus on solving complex system integration issues, achieving timing closure, and developing advanced verification methodologies.

Location: Shanghai

Company

hirify.global is a global leader in electronic design automation (EDA) and intellectual property for the semiconductor industry.

What you will do

• Design, develop, and productize critical protocol products including PCIe and advanced Ethernet.
• Act as an individual contributor on projects involving logic RTL design and UVM-based verification.
• Manage board design, debugging, and technical documentation.
• Resolve complex problems related to protocol and system integration.
• Address electrical or timing closure issues and optimize RTL verification methodologies.

Requirements

• MSEE or equivalent degree.
• Proven experience in logic design and debugging.
• Proficiency in RTL design using Verilog and experience with RTL verification tools.
• Must be located in or able to work in Shanghai.
• Excellent written and verbal communication skills.

Nice to have

• Experience in FPGA design for Xilinx products.
• UVM verification experience.
• Proficiency in scripting languages such as Perl, TCL, or C-shell.

Culture & Benefits

• Opportunity to work on industry-leading flagship emulation and prototyping products.
• Collaborative environment focused on developing leaders and innovators.
• Role with a direct impact on the global technology landscape.