Package Design Engineer (AI)

TL;DR

Package Design Engineer (AI/ASIC): Designing complex flip-chip-BGA packages for industry-leading ASICs with an accent on high-speed SerDes, RF/microwave communications, and AI infrastructure. Focus on optimizing signal integrity, power integrity, and thermal performance for 200G+ SerDes and 3DIC architectures.

Location: Singapore (Yishun)

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions, developing high-performance components for AI, networking, and 5G base stations.

What you will do

• Take overall design responsibility for ASIC package layout and routing.
• Develop critical high-frequency structures for SerDes, ADC/DAC, DDR, and HBM.
• Ensure impedance matching, minimize crosstalk, and optimize signal and power integrity.
• Manage manufacturability, reliability, and thermal aspects of package designs.
• Collaborate with a global R&D team and external vendors across multiple time zones.

Requirements

• Degree in Electrical Engineering (EE/EEE) or a similar field.
• 5+ years of experience (B.Eng) or 3+ years (M.Eng) in flip-chip-BGA package design.
• Proven experience with high-speed SerDes.
• Strong knowledge of package-level signal integrity (SI) and power integrity (PI).
• Experience with Cadence APD (Allegro Package Designer) or equivalent tools.
• Must be located in or able to work in Singapore.

Nice to have

• 8+ years of experience for B.Eng or 6+ years for M.Eng.
• Experience with 2.5D and 3DIC packages.