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Senior/Staff Mid-End Engineer (3D/Process Integration)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Singapore/US/Norway +4 еще
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Senior/Staff Mid-End Engineer (3D/Process Integration) (3DIC/advanced packaging): Defining wafer-on-wafer, chip-on-wafer, or hybrid-bonded 3D stack interfaces for advanced semiconductor products with an accent on TSV, hybrid bonding, thermal-mechanical behavior, and die-to-die SI/PI. Focus on closing 3D signoff, coordinating foundry, memory-partner, and OSAT interfaces, and taking products through tapeout and assembly.

Location: Malaysia / Singapore

Company

hirify.global is a technology company focused on Bitcoin mining infrastructure, ASIC design and manufacturing, datacenters, and AI cloud computing.

What you will do

  • Own the wafer-on-wafer and hybrid-bonding stack definition, including TSV interfaces, bond-pad arrays, keep-outs, and alignment budgets.
  • Drive 3D-aware floorplanning, bump and TSV maps, micro-bump and ballmap planning, and die-to-die interface placement.
  • Define and close DFM and 3D design rules, and lead design-rule and process-assumption reviews.
  • Coordinate thermal and thermal-mechanical analysis, including stress and warpage, and feed mitigations into floorplan, power-delivery, and stack decisions.
  • Drive thermal, SI/PI, and known-good-stack signoff before tapeout, while coordinating the 3D test strategy with DFT.
  • Manage package and substrate co-design handoff to the OSAT, and track foundry and memory-partner deliverables, risks, and milestones.

Requirements

  • BS, MS, or PhD in electrical engineering, materials engineering, mechanical engineering, or a related field.
  • 5+ years of experience in 3DIC, advanced packaging, or process integration, including at least one product taken through tapeout and assembly.
  • Hands-on experience with TSV, hybrid bonding, and a 3D stacking flow such as wafer-on-wafer, chip-on-wafer, SoIC, or CoWoS-class integration.
  • Working knowledge of TSMC 3DFabric or an equivalent foundry 3D ecosystem, including design kits and rule decks.
  • Strong understanding of thermal and thermal-mechanical behavior in stacked die and SI/PI at die-to-die interfaces.
  • Ability to manage cross-organization interfaces with foundries, memory IP partners, and OSATs.

Nice to have

  • Experience with DRAM-on-logic stacks, HBM-class memory integration, or high-bandwidth memory interfaces.
  • Background with AI or HPC accelerators and other high-power, high-bandwidth SoCs.
  • Familiarity with Ansys and 3D physical or signoff flows using Synopsys or Cadence.
  • Experience with stacked-die test, yield debugging, or establishing a 3D-integration methodology on a small team.

Culture & Benefits

  • Inclusive environment that values authenticity and diverse perspectives.
  • Startup-oriented atmosphere with open workspaces and opportunities to connect with industry specialists.
  • Direct contribution to projects in the digital asset and AI infrastructure industries.
  • High autonomy, personal accountability, and opportunities to shape new processes and systems.
  • Training, mentoring, welfare benefits, and professional development opportunities.

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