IP Design Verification Engineer (Silicon)

TL;DR

IP Design Verification Engineer (System Verilog/RTL): Ensuring the functionality and reliability of cutting-edge IP logic designs with an accent on test bench development and high-coverage validation. Focus on replicating and root-causing complex presilicon issues and optimizing verification infrastructure.

Location: Hybrid in Santa Clara, California, USA

Salary: $164,470 – $269,100 USD

Company

hirify.global is a global leader in silicon solutions and semiconductor manufacturing, shaping the future of technology through innovative hardware.

What you will do

• Develop and execute comprehensive IP verification plans aligned with microarchitecture specifications.
• Design and maintain test benches and verification environments for high-coverage validation.
• Implement system simulation models to analyze design functionality, power, and timing.
• Debug and root cause issues in the presilicon environment to drive corrective measures.
• Collaborate with architects and RTL developers to enhance verification of complex features.
• Lead technical reviews and document test plans to ensure robust coverage.

Requirements

• Bachelor's degree with 6+ years of experience (or Master's with 4+, PhD with 2+).
• Proficiency in System Verilog and RTL design.
• Hands-on experience in creating verification test environments and implementing test plans.
• Strong debugging skills for IP microarchitecture validation.
• Must be based in or able to work from Santa Clara, California.

Nice to have

• Experience in group problem-solving within cross-functional teams.
• Familiarity with advanced verification methodologies and tools.
• Proven ability to analyze and improve existing verification infrastructure.

Culture & Benefits

• Competitive total compensation package including stock bonuses.
• Comprehensive health, retirement, and vacation programs.
• Hybrid work model allowing split time between on-site and off-site work.