SoC Verification Engineer (UVM)

TL;DR

SoC Verification Engineer (UVM): Designing and verifying advanced semiconductor solutions for high-quality, scalable products with an accent on UVM-based test benches and AMBA protocols. Focus on developing reusable verification plans, debugging presilicon environments, and integrating security coverage.

Location: Hybrid: Must be based in the US and able to work from hirify.global sites in Austin, TX; Santa Clara, CA; or Hillsboro, OR.

Salary: $141,910.00 - $200,340.00 USD

Company

A global leader in the design and manufacture of semiconductors and computing technology.

What you will do

• Develop UVM-based test benches and execute test cases for complex SoC designs.
• Define scalable and reusable verification plans for blocks, subsystems, and SoC levels.
• Debug and root-cause issues in presilicon environments to ensure functional specifications are met.
• Collaborate with architects, RTL developers, and physical design teams to improve architectural features.
• Integrate security coverage activities and maintain functional verification infrastructure.
• Incorporate feedback from postsilicon development into presilicon verification strategies.

Requirements

• Bachelor's degree in EE, CS, or related field with 4+ years of experience, or a Master's degree with 3+ years of experience.
• Demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.
• Experience with AMBA protocols (CHI, AXI, AHB, APB) and industry-standard VIP from EDA vendors.
• Must be based in the USA to work under the hybrid model at assigned hirify.global sites.

Culture & Benefits

• Competitive compensation package including pay and stock bonuses.
• Comprehensive health and retirement programs.
• Paid vacation and sick leave.
• Hybrid work model allowing a split between on-site and off-site work.