Logic Design Engineer (Networking)

TL;DR

Logic Design Engineer (Networking): Architecting and implementing Ethernet/networking IP for next-generation SoCs in automotive and industrial markets with an accent on IEEE Time Sensitive Networking (TSN) and hardware algorithms. Focus on micro-architecture design, Verilog RTL implementation, and ensuring timing closure for safety-critical applications.

Location: Kanata, Ottawa, Canada (Onsite)

Salary: $96,000 - $132,000 CAD

Company

hirify.global is a global leader in secure connectivity solutions for embedded and connected devices, focusing on automotive, industrial, and IoT markets.

What you will do

• Architect, design, and implement breakthrough Ethernet/networking IP for next-generation SoCs.
• Own the micro-architecture, Verilog RTL implementation, logic synthesis, and timing closure.
• Perform performance, area, and complexity trade-off analysis.
• Conduct front-end to back-end handoff quality checks including Lint, CDC, Synthesis, STA, and LEC.
• Collaborate with design verification engineers to ensure timely delivery of high-quality IP.
• Develop comprehensive functional and implementation specifications.

Requirements

• Bachelors in Computer Science, Engineering or related education required.
• 2+ years of relevant experience in digital design.
• Proficiency in Verilog RTL design, logic synthesis, and timing closure.
• Strong understanding of IP development methodology and front-end design tools.
• Ability to solve system-wide problems and work effectively in a team environment.

Nice to have

• Experience in RTL design of complex digital IP.
• Knowledge of TCP/IP protocols and state-of-the-art networking technologies.
• Experience with data products such as routers, bridges, and switches.
• Expertise in security or cryptography.
• Algorithm development experience.