Principal Engineer - Standard Cell Design (Semiconductor)

TL;DR

Principal Engineer - Standard Cell Design (Semiconductor): Designing and optimizing standard cell libraries to improve power, performance, and area (PPA) across future silicon nodes with an accent on circuit innovation and library architecture. Focus on balancing aggressive Vmin targets, driving DTCO, and collaborating with foundry customers to enable scalable high-performance silicon.

Location: Hybrid. Must be based in the US (California, Arizona, Oregon, or Texas)

Salary: $220,920.00–$311,890.00 USD

Company

A leading semiconductor company providing state-of-the-art manufacturing and foundry services to enable leadership products for the AI era.

What you will do

• Shape standard cell library strategy, including content definition and ecosystem usability.
• Drive circuit innovation for high-performance and low-voltage operation, specifically in sequential and clocking circuits.
• Lead PPA and Vmin optimization efforts across leading-edge process nodes to meet internal and foundry customer needs.
• Partner with DTCO, product design teams, and EDA partners to align on scalable solutions.
• Guide and mentor circuit designers and technical leaders to raise the bar on design quality.
• Analyze silicon and design data to debug issues and refine circuit methodologies.

Requirements

• Ph.D. or Master's degree.
• 10+ years of industry experience in foundation IP design, DTCO, and advanced semiconductor technology.
• In-depth understanding of MOSFET electrical characteristics and transistor device physics at advanced nodes.
• Working knowledge of transistor-level design for static circuits (latches, flops) and standard cell development.
• Experience with standard cell characterization tools and Spice circuit simulations.
• Expertise in low-power, high-performance circuit techniques.

Culture & Benefits

• Hybrid work model allowing a split between on-site and off-site work.
• Competitive total compensation package including stock bonuses.
• Comprehensive benefit programs covering health, retirement, and vacation.
• Opportunity to work on foundation technologies that influence CPU, GPU, and emerging architectures.