Senior Layout Engineer (Semiconductor)

TL;DR

Senior Layout Engineer (Semiconductor): Owning the technical execution of advanced memory IP layouts with an accent on floorplanning, placement, routing, and signoff. Focus on driving technical excellence, resolving complex layout issues, and implementing automation scripts to optimize design cycles in advanced process nodes.

Location: Must be based in Danang, Vietnam (100% on-site)

Company

hirify.global is a global provider of high-performance analog mixed-signal semiconductor IPs powering mobile, automotive, and AI applications.

What you will do

• Own layout design and verification of critical memory IP blocks including floorplanning and routing.
• Troubleshoot and resolve complex layout issues to drive technical improvements.
• Develop automation scripts to accelerate layout cycles and enhance quality.
• Conduct technical reviews and benchmarking of layout deliverables.
• Collaborate with CAD and process teams to optimize layout flows and methodologies.

Requirements

• 5-8+ years of layout experience with proven ability to deliver complex designs.
• Proficiency with layout capture tools like Cadence Virtuoso.
• Experience with verification tools such as Calibre, ICV, or StarRC.
• Familiarity with advanced process nodes like 5nm or 3nm.
• Must be able to work in English with an overseas team.
• B.S. or M.S. in Electrical Engineering or a related field.

Culture & Benefits

• Inspiring environment focused on technical innovation and people well-being.
• Flat management structure encouraging creative thinking and meaningful contributions.
• Commitment to open communication, empathy, and mutual trust.
• Comprehensive compensation package including potential equity and bonuses.
• Full range of medical and financial benefits provided.