Design Verification Engineer (Semiconductors)

TL;DR

Design Verification Engineer (SV/UVM): Developing and executing verification projects for semiconductor designs with an accent on AXI, NOC, and PCIe switch expertise. Focus on building UVM-based test-benches, defining SOC level test plans, and ensuring coverage closure for CPU sub-systems.

Location: Complete On-Site at San Jose, CA

Salary: $95,900 - $149,600

Company

eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services.

What you will do

• Execute complete verification projects as a senior engineer, including technical reviews and client communication.
• Develop UVM-based SV test-benches and define block, sub-system, and SOC top-level test plans.
• Verify PCIe, NVMe, NAND, DDR, and CPU sub-systems.
• Manage regression and coverage closure to ensure design quality.
• Provide guidance and mentoring to junior staff and colleagues.
• Contribute to process improvements and verification methodologies.

Requirements

• 5–7 years of related experience with a 4-year degree (or 3 years with an advanced degree).
• Strong expertise in SV/UVM.
• Expertise in AXI, NOC, Ethernet, PCIe, or UCIe Switches.
• Experience with CPU ARM/RISC-V and C knowledge.
• Must be able to work fully on-site in San Jose, CA.

Culture & Benefits

• Medical, Dental, and Vision Insurance.
• 401k with matching contributions.
• Health Savings Account (HSA) and Health Reimbursement Account (HRA) options.
• Comprehensive Paid Time Off (sick, holiday, vacation).
• Tuition reimbursement and professional growth opportunities.