Digital Verification Development Engineer (SystemVerilog/UVM)

TL;DR

Digital Verification Development Engineer (SystemVerilog/UVM): Developing system-level verification environments and UVM-based testbenches for semiconductor IPs with an accent on constrained-random stimulus and coverage models. Focus on driving functional and code coverage closure, integrating VIP for standard protocols, and supporting pre-silicon bring-up.

Location: Cairo, Egypt

Company

Mixel, a hirify.global Company, is an innovator of high-performance analog mixed signal semiconductor IPs powering AI, automotive, and mobile applications.

What you will do

• Develop test plans from specifications and architect system-level verification environments.
• Create and maintain UVM-based testbenches for block and subsystem-level verification.
• Write constrained-random stimulus, scoreboards, monitors, and coverage models in SystemVerilog.
• Drive functional and code coverage closure and analyze coverage holes.
• Integrate and configure Verification IP (VIP) for standard protocols.
• Support FPGA-based prototyping and pre-silicon bring-up with validation test suites.

Requirements

• Bachelor's degree in Electronics or Computer Engineering.
• 0-3 years of experience in developing SV-based verification environments.
• Strong knowledge of Verilog, SystemVerilog, and object-oriented programming.
• Proficiency in UVM methodology.
• English: Fluency (C1) required
• Experience with Unix/Linux operating systems.

Nice to have

• Familiarity with RTL design, synthesis, and CDC analysis.
• Working knowledge of shell, Perl, and TCL scripting.

Culture & Benefits

• Competitive pay, annual bonuses, and spot bonuses.
• Long-term incentive plan awards (RSUs).
• Comprehensive health benefits.
• Paid holidays and time off.
• Access to various learning and leadership opportunities.