Lead Software Engineer (Logic Synthesis)

TL;DR

Lead Software Engineer (Logic Synthesis): Developing and maintaining the synthesizer for Palladium with an accent on VHDL/Verilog feature support and logic optimization. Focus on improving synthesizer performance and implementing advanced design modeling techniques.

Location: Shanghai (Onsite)

Company

hirify.global is a global leader in electronic design and computational software, focused on solving complex technological challenges.

What you will do

• Develop and maintain the synthesizer for the Palladium platform.
• Implement support for new VHDL and Verilog features.
• Optimize logic and improve overall synthesizer performance.
• Collaborate within multi-site and multi-person project teams.
• Apply attention to detail in complex software development tasks.

Requirements

• Bachelor or Master's degree in EE, CS, or CE.
• 3-5 years of industry experience.
• Proficiency in C/C++ and operating system concepts.
• Experience with design modeling using Verilog, SystemVerilog, VHDL, or SystemC.
• Strong communication skills and ability to work in a collaborative environment.

Nice to have

• Experience in RTL modeling of BFMs.
• Exposure to verification methodologies including UVM and SC/TLM.
• Background in EDA/CAD tool development or logic design verification.
• Experience with AI tools such as Copilot or Claude.

Culture & Benefits

• Opportunity to work on industry-leading technology.
• Collaborative environment with global teams.
• Focus on solving complex, high-impact engineering problems.