Accelerator Compiler Lead (AI)

Accelerator Compiler Lead

Company

Auradine

Conditions

6 days ago LeadSalary: 200K - 500KAnywhere Onsite Full Time Engineering Management Jobs by Auradine

Auradine Auradine is pioneering innovative solutions for world-leading blockchain and cutting-edge AI applications by developing breakthrough technologies like energy-efficient silicon, robust infrastructure, and state-of-the-art software. The company provides Web infrastructure solutions, including their Teraflux™ product line and associated developer tools like the Miner API. Santa Clara, USA Funding Series C ($153M) Series A ($81M) Investors Stanford University DCVC Cota Capital Marathon Digital Holdings Celesta Capital About Auradine Auradine is pioneering innovative solutions for world-leading blockchain and cutting-edge AI applications by developing breakthrough technologies like energy-efficient silicon, robust infrastructure, and state-of-the-art software. Auradine focuses on breakthrough scalability and sustainability for the future of internet infrastructure, enabled by revolutionary blockchain and AI technologies. The company develops complete solutions, including software and silicon systems, and offers its customers both system-level and cloud solutions. Auradine offers a range of products under the Teraflux™ brand, including the AH3880, AT2880, AI3680, AT1500, and AI2500 models, as detailed in their datasheets. They also provide a Teraflux™ Miner API Reference for developers. View jobs by Auradine

Skills

Hardware Synthesis Onnx Llvm Mlir Team Quantization Import Tflite Graph Cpp Ir Codegen Npu Tiling Leadership Scheduling Pytorch Firmware Model Python Optimization Export Accelerator Management Compiler

About the Role

You will own the compiler and model lowering stack for the AI accelerator, including graph import, operator lowering, IR, graph transformations, quantization integration, code generation, graph partitioning, and compiler diagnostics. You will implement architecture and performance features, define executable artifacts, and mentor a team of compiler and ML systems engineers.

Requirements

• Deep experience with compiler development, ML graph compilers, or code generation for accelerators, GPUs, DSPs, or heterogeneous compute systems.
• Strong understanding of ML model formats, graph IRs, operator lowering, tensor layouts, quantization, and runtime/compiler interfaces.
• Strong C++ and Python programming skills and experience building production-quality compiler or systems software.
• Experience with compiler frameworks or technologies such as MLIR, LLVM, TVM, XLA, IREE, Glow, TensorRT-like systems, OpenVINO-like systems, or equivalent.
• Strong understanding of correctness risks in compiler optimizations, graph rewrites, mixed precision, operator fusion, and hardware-specific lowering.
• Ability to work closely with hardware architects, firmware engineers, runtime engineers, model-integration teams, and SQA.
• Experience leading technical teams or major architecture areas.
• Experience with NPU, GPU, DSP, or AI accelerator compiler stacks.
• Experience with quantization-aware compilation, mixed precision, sparsity, pruning, graph partitioning, or hardware-specific scheduling.
• Experience supporting ONNX, PyTorch export, TensorFlow Lite, JAX/XLA, TorchDynamo/TorchInductor, or other model import flows.
• Familiarity with robotics, computer vision, CNNs, transformers, detection, segmentation, depth, SLAM-adjacent perception, or edge AI workloads.
• Experience building customer-facing compiler diagnostics and model-porting tools.
• Experience with model-zoo release processes, accuracy validation, and reproducible benchmark artifacts.
• Open-source compiler contributions or experience working with external framework communities.

Responsibilities

• Lead architecture and development of the AI accelerator compiler stack.
• Own model ingestion and graph lowering from frameworks and exchange formats such as PyTorch export flows, ONNX, TensorFlow Lite, or similar.
• Define operator coverage strategy, lowering rules, graph transformations, fusion, partitioning, and fallback behavior.
• Develop compiler optimization passes for tensor layout, tiling, memory movement, mixed precision, operator fusion, and hardware-specific scheduling.
• Work closely with accelerator runtime and driver teams to define executable artifact formats, metadata, memory planning requirements, profiling hooks, and runtime constraints.
• Partner with hardware architecture and NPU firmware teams on ISA, command streams, tensor layouts, data movement, hardware constraints, and compiler-visible performance features.
• Own quantization compiler integration, including calibration metadata, precision selection, scale handling, layout constraints, and accuracy/performance tradeoffs.
• Build compiler diagnostics that help customers understand unsupported operators, shape constraints, graph rewrites, quantization issues, and performance bottlenecks.
• Establish compiler verification and regression strategy for graph transformations, IR lowering, numerical behavior, model accuracy, and performance.
• Hire, mentor, and lead a team of compiler and ML systems engineers.

Benefits

• Medical dental and vision coverage
• Paid time off
• Flexible work arrangements
• Professional development opportunities
• Equity participation
• Other benefits designed to support the well being and growth of our team

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