Design Verification Engineer (Staff)

TL;DR

Design Verification Engineer (Staff): Verifying complex circuitry for high-speed data infrastructure chips with an accent on System Verilog simulation and RTL debugging. Focus on ensuring design compliance with customer specifications through rigorous testbench development and collaboration with DFT teams.

Location: Must be based in Santa Clara, CA (Onsite)

Salary: $96,570–$144,600 per annum

Company

hirify.global is a semiconductor leader providing essential data infrastructure solutions across enterprise, cloud, and AI architectures.

What you will do

• Verify circuitry for general market and customer-specific chips using System Verilog.
• Run simulations using tools like Synopsys VCS and debug designs until specifications are met.
• Collaborate closely with RTL and DFT engineers throughout the design cycle.
• Present test plans and schedules to review committees for larger design blocks.
• Participate in weekly staff meetings to track progress and resolve technical issues.

Requirements

• Bachelor’s degree in Electrical or Computer Engineering with 2-3 years of experience, or a Master’s/PhD in related fields.
• Coursework in analog circuits, Verilog/VHDL, and computer architecture with a focus on VLSI.
• Proficiency in simulation tools such as Synopsys, Cadence, or Mentor.
• Experience writing and debugging testbenches.
• Comfortable working in a Linux environment and using Python for scripting.
• Must be eligible to access export-controlled information under U.S. law.

Culture & Benefits

• Comprehensive financial well-being programs including an employee stock purchase plan.
• Robust mental health resources and family support programs.
• Recognition and service awards for employee contributions.
• Commitment to professional growth and long-term career development.