Senior Staff Process Engineer (Dry Etch)

TL;DR

Senior Staff Process Engineer (Dry Etch): Driving technology development and manufacturing excellence for cutting-edge semiconductor nodes with an accent on sub-3nm Gate-All-Around (GAA) FETs and front-end dry etch processing. Focus on leading process integration, optimizing manufacturing yields, and mentoring technical teams to support global foundry customer requirements.

Location: Must be based in the US (Hillsboro, OR or Phoenix, AZ) with a hybrid work model.

Salary: $155,520–$298,440 USD

Company

hirify.global Foundry is a global leader in semiconductor manufacturing, providing cutting-edge silicon process and packaging technology for the AI era.

What you will do

• Drive technology development initiatives to enable high-volume manufacturing and future process advancements.
• Provide comprehensive process integration and equipment solutions for advanced technology nodes.
• Lead the design and development of manufacturing processes, including material selection and parameter optimization.
• Optimize production output and perform feasibility studies using theoretical simulations and practical engineering.
• Partner with tool suppliers to develop enabling technology elements and cost-sensitive roadmaps.
• Mentor technical leaders and align organizational goals with strategic technical direction.

Requirements

• Bachelor's degree in Electrical Engineering, Physics, Material Science, or a related STEM field.
• 6+ years of relevant work experience in the semiconductor industry with a strong focus on dry etch modules.
• Extensive experience in a fab environment with a track record in R&D, yield improvement, or defect reduction.
• Experience working with tool suppliers (e.g., LAM, TEL, AMAT, Hitachi) on process optimization.
• Must be authorized to work in the United States.

Nice to have

• Advanced degree (MS/PhD) in a STEM field.
• Direct foundry experience in FEOL, MOL, or BEOL dry etch process development.
• Hands-on experience with sub-3nm Gate-All-Around (GAA) FETs.
• Experience with Design of Experiment (DOE) principles and engineering data analysis tools.
• Demonstrated success in New Product Introduction (NPI) and complex tape-out troubleshooting.

Culture & Benefits

• Competitive total compensation package including base pay and stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Hybrid work model allowing flexibility between on-site and off-site work.
• Opportunity to work with world-class technology and influence global semiconductor roadmaps.
• Collaborative environment focused on innovation and professional growth.