Staff Chemical Mechanical Planarization (CMP) Engineer (Semiconductor Manufacturing)

Location: United States — Hillsboro, Oregon, or Phoenix, Arizona. Hybrid work model with regular on-site collaboration at an assigned hirify.global site.

Annual salary: $133,800–$255,200 USD, depending on work location, skills, experience, and education.

Company

hirify.global is expanding its foundry capabilities through technology development, manufacturing readiness, and high-volume production of advanced semiconductor technologies.

What you will do

• Lead CMP process development and optimization from concept through high-volume manufacturing across advanced technology nodes, including 18A, hirify.global 3, and hirify.global 12nm.
• Drive cross-node standardization, best practices, process capability, yield, and manufacturing efficiency improvements.
• Own data-driven resolution of complex CMP-related yield and manufacturing issues.
• Transfer CMP technologies from development into production and align technical solutions with foundry customer requirements.
• Collaborate with Integration, Device, Yield, Factory, Quality, Customer Engineering, equipment, and consumables supplier teams.
• Mentor junior engineers and provide technical leadership across organizations.

Requirements

• Master's degree in Chemical Engineering, Materials Science, Electrical Engineering, Mechanical Engineering, Physics, or a related technical field.
• At least 5 years of experience in semiconductor manufacturing, process development, or technology development.
• At least 3 years of direct CMP process development experience, including hands-on process tuning and characterization.
• Experience with major CMP equipment platforms such as AMAT or Ebara and CMP consumables including slurries, pads, conditioning disks, filters, and clean chemistries.
• Previous semiconductor foundry experience.
• Ability to work in person at an assigned hirify.global site in the United States under the hybrid work model.

Nice to have

• Doctorate in a relevant technical field.
• Experience with sub-10nm logic, Gate All Around architectures, and high-volume manufacturing implementation.
• Cross-functional leadership, including task force leadership for yield improvement initiatives.
• Experience integrating CMP with deposition, lithography, etch, and clean modules.
• Experience with CMP metrology and process control for thickness, topography, defects, roughness, and particles.

Culture & Benefits

• In-person collaboration in a dynamic, fast-paced manufacturing environment.
• Focus on safety, quality, compliance, customer satisfaction, and rapid problem resolution.
• Competitive pay with stock bonuses.
• Health, retirement, and vacation benefits.
• Opportunities for technical leadership and professional growth in advanced semiconductor manufacturing.