Senior Staff Collateral Design and DFM Engineer

TL;DR

Senior Staff Collateral Design and DFM Engineer (Semiconductor Foundry): Lead cross-functional development of Design for Manufacturability (DFM) methodologies and yield tools to accelerate yield improvement and technology ramp on advanced logic nodes. Focus on translating silicon learning into actionable DTCO/DTCO flow updates, driving scribe line layout and process monitoring structures, and managing design rule development, validation, and waivers to improve performance, yield, and ramp speed.

Location: US, California, Santa Clara (hybrid: split time between on-site at assigned hirify.global site and off-site). Additional locations: US, Arizona, Phoenix; US, Oregon, Hillsboro.

Salary: $161,550.00–317,600.00 USD (annual)

Company

hirify.global’s MDCE organization bridges technology development and high-volume manufacturing to advance semiconductor nodes from qualification to high-yield production.

What you will do

• Lead cross-functional teams across Process Integration, Device, Yield, Design, OPC/RET, Design Rules, DTP, and CAD to define and continuously enhance DFM rules for advanced logic nodes.
• Translate silicon learning and yield insights into actionable feedback for design teams, updating layout and DTCO methodologies to catch yield issues earlier.
• Develop and optimize yield tools and flows for inline yield detection and continuous process optimization in the foundry environment.
• Define and evolve DFM methodologies by analyzing silicon process flows, predicting layout/design marginalities, and creating robust mitigation rules.
• Drive scribe line layout design and process monitoring structure development for advanced node characterization and manufacturing readiness.
• Manage design rule development, validation, and waiver processes to align manufacturing constraints with customer design requirements.

Requirements

• Master’s degree in Electrical Engineering, Physics, or a closely related field.
• 6+ years of experience in DTCO and/or DFM within a semiconductor foundry or advanced technology development environment.
• Experience with DTCO methodologies, including SRAM and Standard Cell design.
• Experience leading cross-functional teams defining derivative architectures covering design rules, transistors, and interconnects.
• Hands-on experience with advanced node test chip design and scribe line optimization across 3nm–16nm FinFET or sub-3nm GAA FET technologies, including Backside Power Delivery (BSPD).

Culture & Benefits

• Hybrid work model: split time between on-site at the assigned hirify.global site and off-site.
• Total compensation package with competitive pay, stock bonuses, and benefits including health, retirement, and vacation.
• Work on advanced semiconductor technologies with direct impact on high-volume production readiness.