Design Engineering Architect (PHY)

TL;DR

Design Engineering Architect (PHY): Contributing to memory interface PHY architecture development with an accent on electrical, timing, power, and protocol considerations. Focus on driving JEDEC-compliant architecture decisions and acting as a customer-facing technical expert for pre-sales and post-delivery support.

Location: San Jose, California

Salary: $136,500–$253,500

Company

hirify.global is a leader in electronic design and computational software, helping innovators solve complex technological challenges.

What you will do

• Contribute to PHY architecture development for memory interface IPs like DDR and LPDDR.
• Drive architecture decisions aligned with JEDEC standards and compliance requirements.
• Act as a customer-facing technical architect for pre-sales, evaluations, and support.
• Collaborate with sales, marketing, and program teams on technical proposals and RFIs.
• Work cross-functionally with design, verification, layout, and silicon validation teams.
• Influence product roadmaps by identifying future standards and customer requirements.

Requirements

• M.S. degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 15 years of industry experience in memory interface PHY or high-speed IO.
• Strong background in memory interface PHYs, JEDEC standards, and protocols.
• Proven ability to own customer-facing technical engagements.
• Excellent written and verbal communication skills.

Culture & Benefits

• Comprehensive medical, dental, and vision plan options.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• Paid vacation and paid holidays.
• Incentive compensation including bonus and equity eligibility.