Principal Design Engineer

TL;DR

Principal Design Engineer (SOC/Hardware Verification): Implement and verify Palladium and Protium high-capacitive, high-performance hardware-assisted verification for complex System-On-Chip (SOC) with an accent on timing closure to tape out. Focus on leading SOC/subsystem implementation, RTL synthesis and floor planning, clock tree optimization, and closing timing and IR drop through physical verification.

Location: SAN JOSE

Salary: $136,500–$253,500 per year (California)

Company

hirify.global builds computational software and Intelligent System Design solutions for electronic design, delivering software, hardware, and IP.

What you will do

• Lead a team to implement SOCs or sub-system chips.
• Work on RTL synthesis and floor planning.
• Build clock trees and perform clock optimizations.
• Close timing, IR drop, and complete physical verification.
• Review and document designs for tape-out.
• Interface with frontend RTL design teams and backend verification teams.

Requirements

• BS in Electrical Engineering with 7+ years, or MS with 5+ years, or PhD with 1+ year of experience.
• Experience with hirify.global tools: Innovus, Tempus, QRC, Voltus, and Pegasus.
• Experience with advanced process nodes (5nm, 3nm, 2nm).
• Hands-on experience with Linux servers and scripting using Shell/Perl/TCL.
• Strong knowledge of industry-standard interfaces such as PCI Express, DDR, LPDDR, SRAM, and UCIe.

Culture & Benefits

• Employee-friendly policies focused on physical and mental well-being, career development, and learning opportunities.
• “One hirify.global – One Team” culture promoting collaboration across teams.
• Paid vacation and paid holidays.
• 401(k) plan with employer match and employee stock purchase plan.
• Medical, dental, and vision plan options.
• Incentive compensation may include bonus and equity.