Junior Senior Physical Design Engineer (CPU)

TL;DR

Junior Senior Physical Design Engineer (CPU): Implementing next-generation CPU cores for client, server, IoT, and AI platforms with an accent on synthesis, place and route (PnR), and physical verification. Focus on analyzing timing and power, resolving design rule compliance issues, and optimizing high-performance, power-efficient processor designs.

Location: On-site in Hillsboro, Oregon, USA

Salary: $105,650 – $172,860 USD

Company

hirify.global is a global leader in semiconductor innovation, developing processors and technology that power the cloud, IoT, and AI platforms.

What you will do

• Execute physical design for CPU core or subsystem blocks, managing the implementation from RTL to GDS.
• Perform synthesis, place and route (PnR), and physical verification tasks.
• Conduct detailed analysis for timing, power, and design rule compliance.
• Debug and resolve complex design issues under the mentorship of senior engineers.
• Develop scripts and flows using TCL and Python to improve design efficiency.
• Collaborate with RTL design, verification, and full-chip integration teams.

Requirements

• Bachelor's degree in Computer/Electrical Engineering with 2+ years of experience, or a Master's degree with 3+ months of experience.
• Experience with IC design tools (Synopsys or Cadence) for logic synthesis, PnR, and static timing analysis.
• Proficiency in PV convergence, including static timing and power analysis.
• Knowledge of physical design verification (DRC/LVS, formal equivalence, electrical rules, noise, and electro-migration).
• Scripting skills in TCL and at least one other language such as Python, Perl, or Ruby.
• Experience with the synthesis of digital logic blocks integrated into large SoCs or IPs.

Nice to have

• Experience with floor-planning, routing techniques, and clock distribution best practices.
• Advanced knowledge of Static Timing Analysis (STA), noise analysis, and reliability verification.
• Familiarity with the Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus).

Culture & Benefits

• Competitive total compensation package including base pay and stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Opportunity to work on industry-leading CPU designs at advanced semiconductor process nodes.
• Culture of inclusion, collaboration, and continuous technical growth.