Asic Verification Engineer (AI)
ΠΡΡΡ & Π‘ΠΎΠΏΡΠΎΠ²ΠΎΠ΄
ΠΠ»Ρ ΠΌΡΡΡΠ° Ρ ΡΡΠΎΠΉ Π²Π°ΠΊΠ°Π½ΡΠΈΠ΅ΠΉ Π½ΡΠΆΠ΅Π½ Plus
ΠΠΏΠΈΡΠ°Π½ΠΈΠ΅ Π²Π°ΠΊΠ°Π½ΡΠΈΠΈ
TL;DR
Asic Verification Engineer (AI/Datacenter): Defining and executing verification for silicon, IP, and subsystem development for next-generation AI infrastructure with an accent on simulation methodology and verification closure. Focus on building scalable verification environments, driving functional signoff for critical silicon blocks, and ensuring tapeout readiness for high-performance computing architecture.
Location: On-site in Santa Clara, CA or Boston, MA
Salary: $120,000β$350,000
Company
An early-stage startup building next-generation infrastructure for AI and datacenter workloads, focusing on advanced silicon and system architecture.
What you will do
- Define and implement verification methodology for IP, subsystem, and SoC-level designs.
- Own verification planning from microarchitecture through design implementation and tapeout.
- Build and maintain scalable verification environments, testbenches, checkers, and coverage models.
- Drive functional verification, coverage closure, debug, and signoff for critical silicon blocks.
- Collaborate with architecture, physical design, and firmware teams to optimize functionality and performance.
- Interface with external IP vendors, foundries, and EDA tool providers to resolve dependencies.
Requirements
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 5+ years of ASIC or SoC verification experience.
- Strong expertise in modern verification methodologies and the full ASIC development lifecycle.
- Hands-on experience with simulation, debug, coverage closure, and regression management.
- Must be able to work on-site in Santa Clara, CA or Boston, MA.
Nice to have
- PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience with SystemVerilog, UVM, constrained-random verification, assertions, or formal verification.
- Knowledge of protocol stacks such as Ethernet, UCIe, UALink, PCIe, or CXL.
- Experience with post-silicon validation, DFT, or manufacturing tests.
- Experience with advanced silicon devices and tapeout processes.
Culture & Benefits
- Opportunity to join an early-stage startup and shape the verification foundation.
- Work on technically ambitious products and solve fundamental infrastructure challenges for AI.
- Collaborative culture that values rigor, clarity, and intellectual fearlessness.
- High level of ownership and impact on product direction and technical execution.
ΠΡΠ΄ΡΡΠ΅ ΠΎΡΡΠΎΡΠΎΠΆΠ½Ρ: Π΅ΡΠ»ΠΈ ΡΠ°Π±ΠΎΡΠΎΠ΄Π°ΡΠ΅Π»Ρ ΠΏΡΠΎΡΠΈΡ Π²ΠΎΠΉΡΠΈ Π² ΠΈΡ ΡΠΈΡΡΠ΅ΠΌΡ, ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡ iCloud/Google, ΠΏΡΠΈΡΠ»Π°ΡΡ ΠΊΠΎΠ΄/ΠΏΠ°ΡΠΎΠ»Ρ, Π·Π°ΠΏΡΡΡΠΈΡΡ ΠΊΠΎΠ΄/ΠΠ, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡΠ΅ ΡΡΠΎΠ³ΠΎ - ΡΡΠΎ ΠΌΠΎΡΠ΅Π½Π½ΠΈΠΊΠΈ. ΠΠ±ΡΠ·Π°ΡΠ΅Π»ΡΠ½ΠΎ ΠΆΠΌΠΈΡΠ΅ "ΠΠΎΠΆΠ°Π»ΠΎΠ²Π°ΡΡΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡΠΈΡΠ΅ Π² ΠΏΠΎΠ΄Π΄Π΅ΡΠΆΠΊΡ. ΠΠΎΠ΄ΡΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β