Design Verification Engineer (AI)

TL;DR

Design Verification Engineer (AI Hardware): Building verification infrastructure for a next-generation AI-native compute platform with an accent on RTL verification and UVM methodologies. Focus on developing testbenches, driving coverage closure, and building verification environments from the ground up for a new AI accelerator architecture.

Location: Onsite in Mountain View, Santa Clara, San Francisco, Santa Barbara, or Los Angeles, CA

Salary: $120,000–$350,000

Company

An early-stage, stealth-mode AI hardware startup building an advanced AI-native compute platform spanning silicon and full-stack infrastructure.

What you will do

• Own block-level RTL verification across an AI accelerator ASIC.
• Build testbenches and drive coverage closure to meet target metrics.
• Leverage AI-assisted tooling flows to accelerate verification timelines.
• Define and build verification infrastructure and methodology from the ground up for a new architecture.

Requirements

• 7+ years of experience verifying complex digital designs at the block or subsystem level.
• Strong expertise in SystemVerilog, UVM, constrained-random verification, and coverage-driven methodologies.
• Hands-on experience with industry-standard simulators (VCS, Xcelium, Riviera, or equivalent).
• Experience using waveform/debug tools such as Verdi or SimVision.
• Demonstrated ability to debug RTL/testbench mismatches.

Nice to have

• SVA assertion development.
• Formal verification methodologies.
• RISC-V architecture experience.
• Experience with emulation platforms.
• Processor or accelerator verification experience.

Culture & Benefits

• High-impact technical ownership in a fast-moving engineering environment.
• Opportunity to help define verification infrastructure for a new compute architecture.
• Work at the intersection of AI systems and advanced silicon development.