Senior Staff Design Engineer (FPGA)

Location: Penang, Malaysia; right to work in Malaysia required

Company

hirify.global develops low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

• Lead the development and validation of models for analog, digital, and mixed-signal circuits.
• Use Verilog, VHDL, SystemVerilog, SPICE, and similar simulation tools for circuit analysis.
• Provide technical leadership and mentorship to circuit modeling engineers.
• Collaborate with design engineers and internal model users to understand requirements and deliver suitable solutions.
• Analyze simulation results and optimize models for accuracy, performance, and efficiency.
• Document modeling processes, assumptions, and results for internal and external stakeholders.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering.
• 10+ years of professional experience.
• Proven experience in circuit modeling and simulation.
• Proficiency with SPICE, Verilog, VHDL, SystemVerilog, or similar tools.
• Strong leadership, analytical, problem-solving, communication, and collaboration skills.
• Successful background and reference checks, plus satisfactory proof of the right to work in Malaysia, are required.

Nice to have

• Experience with data analysis and visualization tools.
• Knowledge of semiconductor devices and circuit design principles.

Culture & Benefits

• International environment with a global workforce of approximately 1,000 employees.
• Focus on research and development, product innovation, and customer service.
• Comprehensive compensation and benefits program.
• Team-first, results-oriented working environment.