FPGA Verification Engineer

TL;DR

FPGA Verification Engineer (Embedded/ASIC): Delivering coverage-closed, verified, and debugged FPGA designs using SystemVerilog and UVM methodologies with an accent on complex system integration and high-performance hardware development. Focus on developing robust verification environments, executing comprehensive test plans, and collaborating with design teams to ensure high-quality deliverables.

Location: Headquartered in Ottawa, Canada.

Salary: $120,000–$170,000 plus bonus and benefits.

Company

hirify.global provides specialized ASIC and FPGA design, verification, and embedded software development services to the electronic design community.

What you will do

• Perform design verification of FPGA-based systems integrating custom logic and 3rd-party IP blocks.
• Develop and maintain verification environments using SystemVerilog and UVM methodologies.
• Create and execute test plans, testbenches, and test cases.
• Debug simulation issues and identify root causes.
• Collaborate with design engineers to ensure high-quality deliverables.
• Perform code and functional coverage analysis and drive closure.

Requirements

• 5+ years of experience in FPGA or ASIC verification.
• Strong knowledge of Verilog / SystemVerilog and hardware design/verification concepts.
• Hands-on experience with UVM / OVM methodologies.
• Experience with simulation tools such as Questa, VCS, or Xcelium.
• Familiarity with constrained random verification, assertions, and functional coverage.
• Understanding of FPGA architectures and toolchains like Xilinx or Intel/Altera.

Nice to have

• Experience with high-speed interfaces and protocols such as PCIe, Ethernet, DDR, or JESD.
• Scripting experience in Python, Perl, or similar.

Culture & Benefits

• Work on challenging, stimulating technical projects with global technology leaders.
• Environment where employees are appreciated, trusted, and engaged.
• Commitment to work-life balance.
• Comprehensive benefits plan.