Lead Application Engineer (Design Verification)

TL;DR

Lead Application Engineer (Design Verification): Driving the adoption of SoC verification and AI solutions by managing technical evaluations and benchmarks for customers with an accent on simulation, emulation, and acceleration. Focus on addressing complex client queries and collaborating with corporate engineering to improve product direction.

Location: Yokohama, Japan

Company

A global leader in electronic design automation (EDA) software tools.

What you will do

• Identify and scope opportunities for SoC Verification, AI, and simulation/emulation products.
• Plan and execute technical evaluations and benchmarks with potential and existing customers.
• Onboard, train, and support customers throughout their projects.
• Deliver advanced trainings, presentations, and technical demonstrations.
• Provide expert technical support to resolve complex client queries.
• Collaborate with corporate engineering and sales teams to influence product direction and improvements.

Requirements

• 4-6+ years of experience in SoC or IP chip-level design using Verilog/VHDL.
• Proficiency in System Verilog/VHDL and HDL simulators.
• Strong verbal and written communication skills in Japanese.
• Business-level English proficiency.
• Experience with formal verification or hardware emulators/accelerators.
• Knowledge of advanced verification methodologies like UVM.

Nice to have

• Experience using Jasper for formal verification.
• Experience applying AI to design and verification processes.

Culture & Benefits

• Opportunity to work at a leading technology company making a global impact.
• Environment focused on developing leaders and innovators.