SoC/IP Design Verification Engineer (UVM)

TL;DR

SoC/IP Design Verification Engineer (UVM): Driving verification for complex SoC/IP blocks with an accent on UVM testbench development, coverage closure, and debug. Focus on architecting scalable verification environments, implementing constrained-random sequences, and ensuring high-quality silicon delivery.

Location: On-site in Guadalajara, Mexico or San Jose, Costa Rica. Must have unrestricted, permanent right to work in Mexico (not eligible for visa or immigration sponsorship).

Company

Global leader in semiconductor design and manufacturing.

What you will do

• Own the full verification lifecycle for IPs, subsystems, or SoC top-level features from requirements to signoff.
• Architect and implement scalable UVM environments, including agents, drivers, monitors, and scoreboards.
• Develop test content using constrained-random sequences, stimulus libraries, and assertions.
• Perform methodical debug across simulation and emulation using waveforms and logs.
• Drive functional and code coverage closure through analysis and implementation of closure strategies.
• Collaborate with RTL design, architecture, and firmware teams to ensure feature completeness.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in SoC/IP design verification.
• Expertise in UVM and SystemVerilog development (testbenches, agents, virtual sequences).
• Proven debug skills using tools such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
• Proficiency in scripting languages like Python and Shell for automation and regressions.
• Advanced English level and unrestricted right to work in Mexico.

Nice to have

• Experience with standard protocols: AXI, ACE, CHI, PCIe, LP/DDR, USB, MIPI, or Ethernet.
• Assertion-based verification (SVA) and formal verification tools like JasperGold or VC Formal.
• Power-aware verification experience using UPF/CPF.
• Experience with emulation or FPGA prototyping (Palladium, Zebu, Veloce).
• Previous experience leading small teams or driving signoff for a tapeout.

Culture & Benefits

• Opportunity to work on high-impact silicon technology in a fast-paced engineering environment.
• Collaborative culture involving cross-functional interaction with architecture and validation teams.
• Focus on continuous improvement of verification flows, CI/CD, and infrastructure.