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2 дня назад

Senior Staff Design Verification Engineer (ASIC)

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Senior Staff Design Verification Engineer (ASIC): Developing end-to-end functional verification for mixed-signal IC solutions with an accent on UVM-based testbenches and block/chip-level design. Focus on creating constrained-random test suites, performing failure analysis, and driving functional coverage closure.

Location: Hybrid (Austin, TX / Chandler, AZ / Greensboro, NC). Candidates must be able to access technical data without a requirement for an export license.

Company

hirify.global is a leader in mixed-signal processing, providing innovative silicon solutions for the world's top consumer brands.

What you will do

  • Develop comprehensive verification plans aligned with design and system requirements.
  • Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions.
  • Perform functional verification of custom mixed-signal ASICs at both block and chip levels.
  • Implement and drive functional and code coverage closure.
  • Conduct failure analysis, regression triage, and debug for functional and timing-related issues.
  • Collaborate cross-functionally with analog/digital designers, firmware teams, and manufacturing test.

Requirements

  • Bachelor’s (10+ years), Master’s (8+ years), or PhD (6+ years) in Electrical Engineering, Computer Engineering, or a related field.
  • Strong proficiency in SystemVerilog with UVM (or OVM/AVM/Vera).
  • Strong proficiency with HDLs including Verilog and/or VHDL.
  • Hands-on experience with testbench architecture, stimulus generation, and regression execution.
  • Ability to access technical data without an export license; no sponsorship provided for licenses.

Nice to have

  • Experience verifying mixed-signal ASICs in complex SoC environments.
  • Knowledge of signal processing concepts relevant to mixed-signal designs.
  • Experience with SystemVerilog Assertions (SVA).
  • Exposure to formal verification, hardware emulation, or acceleration.

Culture & Benefits

  • Award-winning culture built on inclusion, fairness, and meaningful community engagement.
  • Collaborative and technically rigorous work environment.
  • Focus on delivering enjoyable employee experiences and career growth.

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