Senior Principal Engineer (Hardware Application Engineering) (Board & System Design)

TL;DR

Senior Principal Engineer (Hardware Application Engineering) (Board & System Design): Guide customer hardware design-in on hirify.global Ethernet Switch and UALink platforms with an accent on full-lifecycle board and system design quality. Focus on reviewing schematics and PCB stack-ups, defining reference designs, and solving high-speed SI/PI, power, thermal, and bring-up challenges to ensure manufacturable, reliable, high-volume production.

Location: Santa Clara, CA

Salary: $177,820 - $266,400 per annum (USD)

Company

hirify.global builds semiconductor solutions for data infrastructure across enterprise, cloud, and AI.

What you will do

• Serve as senior technical advisor to customer hardware teams designing platforms around hirify.global Ethernet switches and UALink silicon, from early architecture through production ramp.
• Lead design-in reviews of customer schematics, PCB stack-ups, and system architectures; identify risks early and guide best-in-class implementations.
• Define, develop, and support reference designs for new hirify.global silicon, partnering with silicon, packaging, and internal hardware engineering through customer release.
• Own architecture, schematic, layout guidance, and bring-up of hirify.global reference and evaluation platforms; perform root-cause debug during customer lab phases and early production.
• Drive power delivery architecture (PDN design, multi-rail sequencing, decoupling, tolerance analysis), and advise on thermal design and mechanical integration/cooling strategies.
• Provide guidance on signal and power integrity (SI/PI), reliability/manufacturability/testability, and deliver technical training to customers and internal teams.

Requirements

• PhD, Master’s, or Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 15+ years of experience in hardware design, development, and validation of high-speed networking or compute systems.
• 7+ years of dedicated board and system design experience for high-speed platforms using modern SerDes (25G NRZ through 112G/224G PAM4).
• Proven full-lifecycle ownership across architecture, schematic, layout guidance, and bring-up for complex high-speed boards.
• Deep expertise in PCB stack-up/material selection and power architecture for high-current ASICs (PDN, sequencing, decoupling, tolerance analysis).
• Hands-on experience with hardware bring-up, lab debug, and root-cause analysis using industry-standard lab equipment.

Nice to have

• Direct experience with Ethernet switch platforms and/or emerging open AI fabric standards and architectures.
• Experience targeting megascale data center deployments and delivering reference designs for customer enablement.
• Familiarity with ODM/CM manufacturing flows (DFM/DFT, qualification, reliability testing) and advanced cooling approaches (liquid/immersion).
• EDA tool fluency in Cadence (Allegro/Sigrity) or Mentor/Siemens (Xpedition/HyperLynx) ecosystems.

Culture & Benefits

• Comprehensive benefits covering financial well-being, family support, mental and physical health, and recognition.
• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources and service awards to recognize contributions and milestones.
• Travel as needed to customer sites, ODMs, and labs—typically project-driven rather than continuous.

Hiring process

• Interviews evaluate individual experience, thought process, and communication skills in real time.
• Use of AI tools during interviews is not permitted and may result in disqualification.
• Export-controlled technology access may require eligibility review prior to employment.