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6 часов назад

Collateral Design and DFM Engineer (Semiconductors)

190 650 - 269 150$
Формат работы
hybrid
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

Collateral Design and DFM Engineer (Semiconductors): Developing and enhancing Design for Manufacturability (DFM) methodologies to improve performance and yield for advanced logic technologies with an accent on DTCO, silicon learning, and cross-functional leadership. Focus on optimizing layout/DTCO flows, predicting design marginalities, and implementing DFM solutions for sub 3nm GAA FETs and FinFETs.

Location: Hybrid work model at assigned hirify.global sites in the US (Santa Clara, CA; Phoenix, AZ; or Hillsboro, OR)

Salary: $190,650.00-269,150.00 USD

Company

hirify.global Foundry is a global semiconductor manufacturer delivering cutting-edge silicon process and packaging technology for the AI era.

What you will do

  • Lead cross-functional teams to define and enhance DFM rules for advanced logic technologies to improve yield and performance.
  • Analyze silicon learning and yield issues to update layout and DTCO methodologies for early detection of issues.
  • Refine yield tools and flows for inline yield detection and optimization.
  • Develop rules to avoid layout and design marginalities by studying silicon process flows.

Requirements

  • Master or Ph.D. degree in Electrical Engineering, Physics, or a related field.
  • 10+ years of experience in DTCO and/or DFM within a semiconductor foundry or advanced technology development environment.
  • Strong understanding of SRAM, Standard cells, Process Integration, Yield, and Device.
  • Experience leading cross-functional groups in defining derivative architectures (Design rules, transistors, interconnects).
  • Experience in scribe line layout design and process monitoring structure development.
  • Must be eligible to work in a hybrid model at hirify.global US sites.

Nice to have

  • Coding and scripting knowledge.
  • Hands-on experience with 3nm-16nm FinFETs, sub 3nm GAA FETs, and Backside power delivery.
  • Understanding of Physical Design flows for Yield Analysis, DRC, and verification flows.
  • Proficiency in design rule development, validation, and waiver management.

Culture & Benefits

  • Comprehensive total compensation package including competitive pay and stock bonuses.
  • Benefit programs covering health, retirement, and vacation.
  • Hybrid work model allowing a split between on-site and off-site work.

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