SoC Verification Engineer

TL;DR

SoC Verification Engineer (SystemVerilog/UVM): Verification of SoC designs with an accent on UVM/OVM/VMM-based verification methodology and deep validation of high-speed interfaces. Focus on building and executing verification for USB/PCIe/Ethernet with an emphasis on SystemVerilog and strong protocol/interface understanding.

Location: San Jose, CA

Company

hirify.global provides contract engineering staffing for technology roles.

What you will do

• Perform SoC verification using a verification methodology such as UVM, OVM, or VMM.
• Develop and run verification activities for designs involving USB, PCIe, or Ethernet.
• Write and maintain verification components using SystemVerilog.
• Apply interface/protocol knowledge to ensure correct behavior and coverage.
• Contribute to verification planning and execution over a 6–12 month contract.

Requirements

• 7+ years of experience in verification.
• Experience with verification methodology: UVM, OVM, or VMM (any one workable).
• Very good experience with either USB, PCIe, or Ethernet.
• Experience with SystemVerilog.
• Understanding of ONFI, NVMe, and SERDES is required to be considered a major plus.

Culture & Benefits

• Contract engagement for 6–12 months.
• Work location: San Jose, CA.
• Role focuses on hands-on verification engineering and interface validation.