CPU Core Design Verification Testbench Lead (RISC-V)

Location: Hybrid, based in Austin, Texas, or Santa Clara, California, United States

Company

Tenstorrent develops high-performance RISC-V CPUs and AI compute platforms spanning software, compilers, networking, and semiconductors.

What you will do

• Lead hands-on core-level testbench development for high-performance out-of-order RISC-V CPU cores.
• Own and evolve CVM-based verification methodology, infrastructure, and reusable testbench components.
• Plan and drive functional verification for CPU features, ISA behavior, and microarchitectural scenarios.
• Develop UVM, assembly, C/C++ stimulus, and C++ functional models for RISC-V extensions, APIC, and IOMMU components.
• Debug regressions, close coverage, and improve core-, cluster-, and chip-level testbenches across simulation, emulation, and post-silicon environments.
• Build Python and AI-assisted tooling for triage and root-cause analysis across logs, waveforms, and verification databases.

Requirements

• 8+ years of experience in CPU verification, CPU testbench development, or closely related digital design.
• Deep hands-on experience building and owning CPU core-level testbenches.
• Strong knowledge of high-performance out-of-order CPU microarchitecture.
• Experience with CVM methodology; UVM experience is strongly preferred.
• Ability to work across RTL, waveforms, logs, regressions, and cross-functional debug with design, DV, emulation, and post-silicon teams.
• Experience using AI-assisted verification workflows with sound engineering judgment to validate results.

Nice to have

• Experience developing C++ functional models for RISC-V extensions and un-core components.
• Experience spanning pre-silicon, emulation, and post-silicon verification with shared stimulus.

Culture & Benefits

• Collaborative, curious environment focused on solving challenging technical problems.
• Opportunity to work on open, high-performance compute for real workloads and developers.
• Exposure to CPU core, cluster, and chip-level verification across the broader compute roadmap.
• Employment is contingent on eligibility to access U.S. export-controlled technology.
• Access to export-controlled information may depend on citizenship, permanent residency, or prior U.S. government license approval.