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Principal Device Engineer (Semiconductors)

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
UK
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR

Principal Device Engineer (Semiconductors): Leading the TCAD-driven development and optimization of Power Trench MOSFET technologies with an accent on device physics, simulation accuracy, and performance trade-offs. Focus on shaping next-generation device architectures, influencing early-stage product decisions, and bridging the gap between simulation insights and industrial-scale manufacturing.

Location: Must be based in or able to work from Manchester, UK (Hybrid role).

Company

hirify.global is a global leader in the production of essential semiconductors and components, committed to innovation in power electronics and sustainable manufacturing.

What you will do

  • Lead the TCAD-driven development and optimization of Power Trench MOSFET architectures.
  • Perform electrostatic, thermal, and reliability simulations to guide device design decisions.
  • Translate simulation outcomes into actionable process, layout, and structural requirements.
  • Support technology roadmaps through quantitative feasibility studies and trade-off analysis.
  • Troubleshoot device-level issues across development and production cycles.
  • Collaborate with Process Integration, Product Development, and Foundry partners to drive innovation.

Requirements

  • MSc or PhD in Electrical Engineering, Physics, or a related field.
  • Several years of professional experience in device engineering and TCAD-based technology development.
  • Deep expertise with TCAD tools, specifically Synopsys Sentaurus.
  • Strong understanding of semiconductor device physics and Power MOSFET architectures.
  • Ability to analyze performance, reliability, and manufacturability trade-offs.
  • Strong analytical, problem-solving, and technical communication skills.

Nice to have

  • PhD focused on power semiconductor devices.
  • Industrial or foundry experience in Power MOSFET technology.
  • Experience with process integration or layout-driven device optimization.
  • Knowledge of high-field effects, ruggedness (UIS), and reliability mechanisms.

Culture & Benefits

  • 33 days of annual leave plus flexible working arrangements.
  • Contributory pension scheme up to 9% and 12x salary life assurance.
  • Annual Incentive Plan of up to 20%.
  • Opportunities for funded academic support up to PhD level.
  • On-site medical centre and enhanced parental leave.
  • Commitment to diversity and inclusion with dedicated employee resource groups.

Hiring process

  • Recruiter review.
  • Teams interview.
  • Final on-site or virtual interview and assessment.

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